GP

Guillaume Plassan

SY Synopsys: 2 patents #669 of 2,302Top 30%
Overall (All Time): #1,863,357 of 4,157,543Top 45%
2
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
11526641 Formal gated clock conversion for field programmable gate array (FPGA) synthesis Lisa McIlwain, Fahim Rahim, Dipti Ranjan Senapati 2022-12-13
10599800 Formal clock network analysis, visualization, verification and generation Mohamed Shaker Sarwary, Hans-Joerg Peter, Barsneya Chakrabarti, Mohammad H. Movahed-Ezazi 2020-03-24