Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11526641 | Formal gated clock conversion for field programmable gate array (FPGA) synthesis | Fahim Rahim, Guillaume Plassan, Dipti Ranjan Senapati | 2022-12-13 |
| 10643012 | Concurrent formal verification of logic synthesis | Michael S. Quayle, Eyal Odiz, Patrick Groeneveld, John W. Hagerman, Kshama Jambhekar +1 more | 2020-05-05 |
| 8650513 | Reducing x-pessimism in gate-level simulation and verification | Arturo Salz, Guillermo Maturana, In-Ho Moon | 2014-02-11 |
| 6668362 | Hierarchical verification for equivalence checking of designs | Demosthenes Anastasakis, Slawomir PILARSKI | 2003-12-23 |