Issued Patents All Time
Showing 1–3 of 3 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10643012 | Concurrent formal verification of logic synthesis | Lisa McIlwain, Michael S. Quayle, Eyal Odiz, John W. Hagerman, Kshama Jambhekar +1 more | 2020-05-05 |
| 6505328 | Method for storing multiple levels of design data in a common database | Lukas P. P. P. van Ginneken, Wilhelmus J. M. Philipsen | 2003-01-07 |
| 6230304 | Method of designing a constraint-driven integrated circuit layout | Lukas P. P. P. van Ginneken | 2001-05-08 |