Issued Patents All Time
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9811624 | Timing closure methodology including placement with initial delay values | Prabhakar Kudva | 2017-11-07 |
| 8621403 | Timing closure methodology including placement with initial delay values | Prabhakar Kudva | 2013-12-31 |
| 7103863 | Representing the design of a sub-module in a hierarchical integrated circuit design and analysis system | Michael Riepe, Robert M. Swanson, Timothy Michael Burks, Karen F. Vahtra, Hamid Savoj | 2006-09-05 |
| 6845494 | Method for generating design constraints for modules in a hierarchical integrated circuit design system | Timothy Michael Burks, Michael Riepe, Hamid Savoj, Robert M. Swanson, Karen E. Vahtra | 2005-01-18 |
| 6725438 | Timing closure methodology | — | 2004-04-20 |
| 6553338 | Timing optimization in presence of interconnect delays | Premal Buch, Hamid Savoj | 2003-04-22 |
| 6505328 | Method for storing multiple levels of design data in a common database | Patrick Groeneveld, Wilhelmus J. M. Philipsen | 2003-01-07 |
| 6496965 | Automated design of parallel drive standard cells | Raymond Nijssen, Premal Buch | 2002-12-17 |
| 6453446 | Timing closure methodology | — | 2002-09-17 |
| 6378114 | Method for the physical placement of an integrated circuit adaptive to netlist changes | Narendra V. Shenoy | 2002-04-23 |
| 6230304 | Method of designing a constraint-driven integrated circuit layout | Patrick Groeneveld | 2001-05-08 |