Issued Patents All Time
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9559907 | Remote verification for configuration updates | Sandilya Garimella | 2017-01-31 |
| 9203698 | Remote verification for configuration updates | Sandilya Garimella | 2015-12-01 |
| 8898748 | Remote verification for configuration updates | Sandilya Garimella | 2014-11-25 |
| 7970590 | Parametric timing analysis | — | 2011-06-28 |
| 7346874 | Parametric timing analysis | — | 2008-03-18 |
| 7103863 | Representing the design of a sub-module in a hierarchical integrated circuit design and analysis system | Michael Riepe, Robert M. Swanson, Lukas P. P. P. van Ginneken, Karen F. Vahtra, Hamid Savoj | 2006-09-05 |
| 6845494 | Method for generating design constraints for modules in a hierarchical integrated circuit design system | Michael Riepe, Hamid Savoj, Robert M. Swanson, Karen E. Vahtra, Lukas P. P. P. van Ginneken | 2005-01-18 |
| 6601220 | Method for transistor-level calculation of the precharge time of domino logic circuits with unlocked evaluation paths | David H. Allen, Gregory Allen Wetli | 2003-07-29 |
| 6185723 | Method for performing timing analysis of a clock-shaping circuit | Robert E. Mains | 2001-02-06 |
| 6014510 | Method for performing timing analysis of a clock circuit | Robert E. Mains | 2000-01-11 |
| 5946475 | Method for performing transistor-level static timing analysis of a logic circuit | Robert E. Mains | 1999-08-31 |