Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8732638 | Verifying proper representation of semiconductor device fingers | Binhuai Brian Fa, Kuldeep Singh, Bruce M. K. Leong, Kong-Fai Woo | 2014-05-20 |
| 8380656 | Technique for fast power estimation using probabilistic analysis of combinational logic | Krishnan Sundaresan, Wei-Lun Hung, Jaewon Oh | 2013-02-19 |
| 7958474 | Highly threaded static timer | George J. Chen, Gilda Garreton, Steven M. Rubin | 2011-06-07 |
| 7802217 | Leakage power optimization considering gate input activity and timing slack | Venkatesh P. Gopinath, Krishnan Sundaresan, Jaewon Oh, Ke-Ou Peng | 2010-09-21 |
| 7797658 | Multithreaded static timing analysis | George J. Chen, Darryl J. Gove | 2010-09-14 |
| 7216316 | Method for evaluating nets in crosstalk noise analysis | Jeannette Sutherland, Matthew J. Amatangelo, Shervin Hojat | 2007-05-08 |
| 7206958 | Determining cycle adjustments for static timing analysis of multifrequency circuits | Jeannette Sutherland, Matthew J. Amatangelo | 2007-04-17 |
| 7051305 | Delay estimation using edge specific miller capacitances | Hien T. Ha, George J. Chen | 2006-05-23 |
| 6185723 | Method for performing timing analysis of a clock-shaping circuit | Timothy Michael Burks | 2001-02-06 |
| 6014510 | Method for performing timing analysis of a clock circuit | Timothy Michael Burks | 2000-01-11 |
| 5946475 | Method for performing transistor-level static timing analysis of a logic circuit | Timothy Michael Burks | 1999-08-31 |
| 5771375 | Automatic delay adjustment for static timing analysis using clock edge identification and half cycle paths | — | 1998-06-23 |