Issued Patents All Time
Showing 1–25 of 51 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12432936 | Capacitor integrated with memory element of memory cell | Joseph Versaggi, Gregory A. Northrop, Bipul C. Paul | 2025-09-30 |
| 12426278 | Resistive memory elements accessed by bipolar junction transistors | Alexander M. Derrickson, Hongru Ren | 2025-09-23 |
| 12407350 | Voltage level shifter with programmable high supply voltage and high supply voltage-dependent variable low supply voltage | Siva Kumar Chinthu, Suresh Pasupula, Devesh Dwivedi | 2025-09-02 |
| 12386379 | Non-volatile current mirror circuit with programmable transistor | Navneet Jain | 2025-08-12 |
| 12376315 | Resistive memory element arrays with shared electrode strips | Bipul C. Paul, Xiaoli Hu | 2025-07-29 |
| 12283952 | Voltage level shifter with multi-step programmable high supply voltage and high supply voltage-dependent variable low supply and gate bias voltages | Siva Kumar Chinthu, Suresh Pasupula, Devesh Dwivedi | 2025-04-22 |
| 12211585 | Partitioned memory architecture with single resistor memory elements for in-memory serial processing | Pirooz Parvarandeh | 2025-01-28 |
| 12205633 | Non-volatile memory device with reference voltage circuit including column(s) of reference bit cells adjacent columns of memory bit cells within a memory cell array | Xiaoli Hu, Thomas Melde, Nicki N. Mika | 2025-01-21 |
| 12190930 | Threshold voltage-programmable field effect transistor-based memory cells and look-up table implemented using the memory cells | Pirooz Parvarandeh | 2025-01-07 |
| 12176023 | Non-volatile static random access memory bit cells with ferroelectric field-effect transistors | Pirooz Parvarandeh, Navneet Jain, Bipul C. Paul, Halid Mulaosmanovic | 2024-12-24 |
| 12159685 | Partitioned memory architecture and method for repeatedly using the architecture for multiple in-memory processing layers | Pirooz Parvarandeh | 2024-12-03 |
| 12136468 | Calibration methods and structures for partitioned memory architecture with single resistor or dual resistor memory elements | Pirooz Parvarandeh | 2024-11-05 |
| 12125530 | Partitioned memory architecture with single resistor or dual resistor memory elements for in-memory pipeline processing | Pirooz Parvarandeh | 2024-10-22 |
| 12106804 | Partitioned memory architecture with dual resistor memory elements for in-memory serial processing | Pirooz Parvarandeh | 2024-10-01 |
| 12027226 | Structure including a cross-bar router and method | Navneet Jain, Sven Beyer | 2024-07-02 |
| 11990171 | Threshold voltage-programmable field effect transistor-based memory cells and look-up table implemented using the memory cells | Pirooz Parvarandeh | 2024-05-21 |
| 11855642 | Programmable delay circuit including threshold-voltage programmable field effect transistor | Navneet Jain | 2023-12-26 |
| 11056646 | Memory device having programmable impedance elements with a common conductor formed below bit lines | Mark T. Ramsbey, Jeffrey A. Shields, Kuei-Chang Tsai, Chakravarthy Gopalan, Michael A. Van Buskirk | 2021-07-06 |
| 10984861 | Reference circuits and methods for resistive memories | Ishai Naveh, John Dinh, Mark T. Ramsbey | 2021-04-20 |
| 10777268 | Static random access memories with programmable impedance elements and methods and devices including the same | Nathan Gonzales | 2020-09-15 |
| 10181496 | Programmable impedance memory device and related methods | Ming Sang Kwan | 2019-01-15 |
| 9818939 | Resistive switching devices having a switching layer and an intermediate electrode layer and methods of formation thereof | John Ross Jameson, John Sanchez, Wei Ti Lee, Yi Ma, Foroozan Sarah Koushan | 2017-11-14 |
| 9530495 | Resistive switching memory having a resistor, diode, and switch memory cell | John Dinh, Nathan Gonzales, Derric Lewis, Deepak Kamalanathan, Ming Sang Kwan | 2016-12-27 |
| 9524777 | Dual program state cycling algorithms for resistive switching memory device | Deepak Kamalanathan, Ming Sang Kwan, John Ross Jameson | 2016-12-20 |
| 9472272 | Resistive switching memory with cell access by analog signal controlled transmission gate | Deepak Kamalanathan, Daniel Wang | 2016-10-18 |