Issued Patents All Time
Showing 1–25 of 42 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11069699 | NAND memory cell string having a stacked select gate structure and process for forming same | Shenqing Fang, Youseok Suh, Michael A. Van Buskirk | 2021-07-20 |
| 10756101 | NAND memory cell string having a stacked select gate structure and process for for forming same | Shenqing Fang, Youseok Suh, Michael A. Van Buskirk | 2020-08-25 |
| 10566341 | NAND memory cell string having a stacked select gate structure and process for for forming same | Shenqing Fang, Youseok Suh, Michael A. Van Buskirk | 2020-02-18 |
| 10361215 | NAND memory cell string having a stacked select gate structure and process for for forming same | Shenqing Fang, Youseok Suh, Michael A. Van Buskirk | 2019-07-23 |
| 10181496 | Programmable impedance memory device and related methods | Venkatesh P. Gopinath | 2019-01-15 |
| 10038004 | NAND memory cell string having a stacked select gate structure and process for for forming same | Shenqing Fang, Youseok Suh, Michael A. Van Buskirk | 2018-07-31 |
| 9530495 | Resistive switching memory having a resistor, diode, and switch memory cell | John Dinh, Venkatesh P. Gopinath, Nathan Gonzales, Derric Lewis, Deepak Kamalanathan | 2016-12-27 |
| 9524777 | Dual program state cycling algorithms for resistive switching memory device | Deepak Kamalanathan, Venkatesh P. Gopinath, John Ross Jameson | 2016-12-20 |
| 9437815 | Resistive switching memory device architecture for reduced cell damage during processing | — | 2016-09-06 |
| 9368206 | Capacitor arrangements using a resistive switching memory cell structure | John Dinh, Venkatesh P. Gopinath, Derric Lewis, Shane Hollmer, John Ross Jameson +1 more | 2016-06-14 |
| 9171936 | Barrier region underlying source/drain regions for dual-bit memory devices | Shankar Sinha, Yi He, Zhizheng Liu | 2015-10-27 |
| 8559255 | Controlling AC disturbance while programming | Sung-Yong Chung, Zhizheng Liu, Yugi Mizuguchi, Xuguang Wang, Yi He +4 more | 2013-10-15 |
| 8404541 | Strapping contact for charge protection | Wei Zheng, Jean Y. Yang, Mark Randolph, Yi He, Zhizheng Liu +1 more | 2013-03-26 |
| 8264898 | Controlling AC disturbance while programming | Sung-Yong Chung, Zhizheng Liu, Yugi Mizuguchi, Xuguang Wang, Yi He +4 more | 2012-09-11 |
| 7986562 | Controlling AC disturbance while programming | Sung-Yong Chung, Zhizheng Liu, Yugi Mizuguchi, Xuguang Wang, Yi He +4 more | 2011-07-26 |
| 7977218 | Thin oxide dummy tiling as charge protection | Cinti X. Chen, Yi He, Wenmei Li, Zhizheng Liu, Yu Sun +1 more | 2011-07-12 |
| 7888218 | Using thick spacer for bitline implant then remove | Zhizheng Liu, Shankar Sinha, Timothy Thurgate | 2011-02-15 |
| 7750407 | Strapping contact for charge protection | Wei Zheng, Jean Y. Yang, Mark Randolph, Yi He, Zhizheng Liu +1 more | 2010-07-06 |
| 7713875 | Variable salicide block for resistance equalization in an array | Michael Brennan, Yi He, Mark Randolph | 2010-05-11 |
| 7679967 | Controlling AC disturbance while programming | Sung-Yong Chung, Zhizheng Liu, Yugi Mizuguchi, Xuguang Wang, Yi He +4 more | 2010-03-16 |
| 7671405 | Deep bitline implant to avoid program disturb | Timothy Thurgate, Yi He, Zhizheng Liu, Xuguang Wang | 2010-03-02 |
| 7626869 | Multi-phase wordline erasing for flash memory | Xuguang Wang, Yi He, Zhizheng Liu, Sung-Yong Chung, Darlene Hamilton +4 more | 2009-12-01 |
| 7599228 | Flash memory device having increased over-erase correction efficiency and robustness against device variations | Qiang Lu, Kuo-Tung Chang, Kazuhiro Mizutani, Sung-chul Lee, Sheung-Hee Park | 2009-10-06 |
| 7561471 | Cycling improvement using higher erase bias | Sheung-Hee Park, Xuguang Wang, Wing Leung, Yi He, Edward Franklin Runnion | 2009-07-14 |
| 7553727 | Using implanted poly-1 to improve charging protection in dual-poly process | Bradley Marc Davis, Jean Y. Yang, Zhizheng Liu, Yi He | 2009-06-30 |