| 9318333 |
Dielectric extension to mitigate short channel effects |
Vidyut Gopal, Shankar Sinha, Phillip Jones |
2016-04-19 |
$2,645,000 |
| 8673716 |
Memory manufacturing process with bitline isolation |
Mark T. Ramsbey, Tazrien Kamal, Emmanuil Lingunis, Hidehiko Shiraiwa, Yu Sun |
2014-03-18 |
$3,810,000 |
| 8415734 |
Memory device protection layer |
Rinji Sugino, Timothy Thurgate, Michael Brennan |
2013-04-09 |
$2,664,000 |
| 8404541 |
Strapping contact for charge protection |
Wei Zheng, Mark Randolph, Ming Sang Kwan, Yi He, Zhizheng Liu +1 more |
2013-03-26 |
$2,910,000 |
| 7977218 |
Thin oxide dummy tiling as charge protection |
Cinti X. Chen, Yi He, Wenmei Li, Zhizheng Liu, Ming Sang Kwan +1 more |
2011-07-12 |
$1,106,000 |
| 7750407 |
Strapping contact for charge protection |
Wei Zheng, Mark Randolph, Ming Sang Kwan, Yi He, Zhizheng Liu +1 more |
2010-07-06 |
$561,000 |
| 7696094 |
Method for improved planarization in semiconductor devices |
David Matsumoto, Michael Brennan, Vidyut Gopal |
2010-04-13 |
$12,774,000 |
| 7553727 |
Using implanted poly-1 to improve charging protection in dual-poly process |
Ming Sang Kwan, Bradley Marc Davis, Zhizheng Liu, Yi He |
2009-06-30 |
|
| 7432178 |
Bit line implant |
Angela T. Hui, Yu Sun, Mark T. Ramsbey, Weidong Qian |
2008-10-07 |
|
| 7307027 |
Void free interlayer dielectric |
Minh Van Ngo, Alexander H. Nickel, Hieu Pham, Hirokazu Tokuno, Weidong Qian |
2007-12-11 |
|
| 7163860 |
Method of formation of gate stack spacer and charge storage materials having reduced hydrogen content in charge trapping dielectric flash memory device |
Tazrien Kamal, Yun Wu, Mark T. Ramsbey, Arvind Halliyal, Rinji Sugino +2 more |
2007-01-16 |
$6,080,000 |
| 7115469 |
Integrated ONO processing for semiconductor devices using in-situ steam generation (ISSG) process |
Arvind Halliyal, Mark T. Ramsbey, Hidehiko Shiraiwa |
2006-10-03 |
$7,557,000 |
| 7098546 |
Alignment marks with salicided spacers between bitlines for alignment signal improvement |
Emmanuil H. Lingunis, Hidehiko Shiraiwa |
2006-08-29 |
|
| 7078749 |
Memory structure having tunable interlayer dielectric and method for fabricating same |
Yider Wu |
2006-07-18 |
$7,454,000 |
| 7052961 |
Method for forming wordlines having irregular spacing in a memory array |
Hidehiko Shiraiwa, Jaeyong Park, Cyrus E. Tabery |
2006-05-30 |
$8,404,000 |
| 7033957 |
ONO fabrication process for increasing oxygen content at bottom oxide-substrate interface in flash memory devices |
Hidehiko Shiraiwa, Tazrien Kamal, Mark T. Ramsbey, Inkuk Kang, Jaeyong Park +4 more |
2006-04-25 |
|
| 7023046 |
Undoped oxide liner/BPSG for improved data retention |
Minh Van Ngo, Angela T. Hui, Ning Cheng, Jeyong Park, Robert A. Huertas +3 more |
2006-04-04 |
$14,413,000 |
| 7018868 |
Disposable hard mask for memory bitline scaling |
Jeff P. Erhardt, Cyrus E. Tabery, Weidong Qian, Mark T. Ramsbey, Jaeyong Park +1 more |
2006-03-28 |
$11,294,000 |
| 6994939 |
Semiconductor manufacturing resolution enhancement system and method for simultaneously patterning different feature types |
Kouros Ghandehari, Christopher A. Spence |
2006-02-07 |
$12,481,000 |
| 6989563 |
Flash memory cell with UV protective layer |
Krishnashree Achuthan, Patrick K. Cheung, Cyrus E. Tabery, Ning Cheng, Minh Van Ngo |
2006-01-24 |
$11,964,000 |
| 6989320 |
Bitline implant utilizing dual poly |
Weidong Qian, Mark T. Ramsbey, Sameer Haddad |
2006-01-24 |
$11,964,000 |
| 6987048 |
Memory device having silicided bitlines and method of forming the same |
Ning Cheng, Hiroyuki Kinoshita, Jeff P. Erhardt, Mark T. Ramsbey, Cyrus E. Tabery |
2006-01-17 |
$20,825,000 |
| 6969886 |
ONO fabrication process for reducing oxygen vacancy content in bottom oxide layer in flash memory devices |
Jaeyong Park, Hidehiko Shiraiwa, Arvind Halliyal, Inkuk Kang, Tazrien Kamal +1 more |
2005-11-29 |
|
| 6955965 |
Process for fabrication of nitride layer with reduced hydrogen content in ONO structure in semiconductor device |
Arvind Halliyal, Tazrien Kamal, Hidehiko Shiraiwa |
2005-10-18 |
|
| 6949481 |
Process for fabrication of spacer layer with reduced hydrogen content in semiconductor device |
Arvind Halliyal, Fred Cheung, Rinji Sugino, Hidehiko Shiraiwa, Tazrien Kamal |
2005-09-27 |
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