Issued Patents All Time
Showing 1–25 of 34 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11430689 | Inter-layer insulator for electronic devices and apparatus for forming same | Fei Wang | 2022-08-30 |
| 10256137 | Self-aligned trench isolation in integrated circuits | Ching-Huang Lu, Lei Xue, Kenichi Ohtsuka, Simon S. Chan | 2019-04-09 |
| 10020317 | Memory device with multi-layer channel and charge trapping layer | Renhua Zhang, Lei Xue, Krishnaswamy Ramkumar | 2018-07-10 |
| 9831114 | Self-aligned trench isolation in integrated circuits | Ching-Huang Lu, Lei Xue, Kenichi Ohtsuka, Simon S. Chan | 2017-11-28 |
| 9493874 | Distribution of gas over a semiconductor wafer in batch processing | — | 2016-11-15 |
| 9437470 | Self-aligned trench isolation in integrated circuits | Ching-Huang Lu, Lei Xue, Kenichi Ohtsuka, Simon S. Chan | 2016-09-06 |
| 9252221 | Formation of gate sidewall structure | Scott A. Bell, Chun Chen, Shenging Fang | 2016-02-02 |
| 9252026 | Buried trench isolation in integrated circuits | Lei Xue, Ching-Huang Lu, Simon S. Chan | 2016-02-02 |
| 8987092 | Methods for fabricating memory cells having fin structures with semicircular top surfaces and rounded top corners and edges | Inkuk Kang, Gang Xue, Shenqing Fang, Yi Ma | 2015-03-24 |
| 8809206 | Patterned dummy wafers loading in batch type CVD | Bradley Marc Davis, Lei Xue, Kenichi Ohtsuka | 2014-08-19 |
| 8809936 | Memory cell system with multiple nitride layers | Lei Xue, Youseok Suh, Hidehiko Shiraiwa, Meng Ding, Shenqing Fang +1 more | 2014-08-19 |
| 8647969 | Method for forming a semiconductor layer with improved gap filling properties | Yider Wu, Minh Van Ngo, Jeffrey S. Glick, Kuo-Tung Chang | 2014-02-11 |
| 8455268 | Gate replacement with top oxide regrowth for the top oxide improvement | Chungho Lee, Hiroyuki Kinoshita, Kuo-Tung Chang, Chi Chang, Huaqiang Wu | 2013-06-04 |
| 8415734 | Memory device protection layer | Timothy Thurgate, Jean Y. Yang, Michael Brennan | 2013-04-09 |
| 8143661 | Memory cell system with charge trap | Shenqing Fang, Jayendra D. Bhakta, Takashi Orimoto, Hiroyuki Nansei, Yukio Hayakawa +8 more | 2012-03-27 |
| 8133801 | Method for forming a semiconducting layer with improved gap filling properties | Yider Wu, Minh Van Ngo, Jeffrey S. Glick, Kuo-Tung Chang | 2012-03-13 |
| 7998846 | 3-D integrated circuit system and method | Eunha Kim, Jeremy A. Wahl, Shenqing Fang, Youseok Suh, Kuo-Tung Chang +2 more | 2011-08-16 |
| 7354826 | Method for forming memory array bitlines comprising epitaxially grown silicon and related structure | Takashi Orimoto, Robert B. Ogle | 2008-04-08 |
| 7297592 | Semiconductor memory with data retention liner | Minh Van Ngo, Arvind Halliyal, Tazrien Kamal, Hidehiko Shiraiwa, Dawn Hopper +1 more | 2007-11-20 |
| 7220643 | System and method for gate formation in a semiconductor device | Hajime Wada, Jaeyong Park, Hirokazu Tokuno | 2007-05-22 |
| 7163860 | Method of formation of gate stack spacer and charge storage materials having reduced hydrogen content in charge trapping dielectric flash memory device | Tazrien Kamal, Yun Wu, Mark T. Ramsbey, Jean Y. Yang, Arvind Halliyal +2 more | 2007-01-16 |
| 7151028 | Memory cell with plasma-grown oxide spacer for reduced DIBL and Vss resistance and increased reliability | Shenqing Fang, Kuo-Tung Chang, Zhigang Wang, Kazuhiro Mizutani, Pavel Fastenko | 2006-12-19 |
| 7074677 | Memory with improved charge-trapping dielectric layer | Arvind Halliyal, Minh Van Ngo, Hidehiko Shiraiwa | 2006-07-11 |
| 7033957 | ONO fabrication process for increasing oxygen content at bottom oxide-substrate interface in flash memory devices | Hidehiko Shiraiwa, Tazrien Kamal, Mark T. Ramsbey, Inkuk Kang, Jaeyong Park +4 more | 2006-04-25 |
| 7026211 | Semiconductor component and method of manufacture | Joong S. Jeon, Robert B. Ogle | 2006-04-11 |