Issued Patents All Time
Showing 25 most recent of 42 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9318373 | Method and apparatus for protection against process-induced charging | David Michael Rogers, Mimi Qian, Kwadwo Appiah, Mark Randolph, Michael VanBuskirk +3 more | 2016-04-19 |
| 8673716 | Memory manufacturing process with bitline isolation | Mark T. Ramsbey, Jean Y. Yang, Emmanuil Lingunis, Hidehiko Shiraiwa, Yu Sun | 2014-03-18 |
| 8445966 | Method and apparatus for protection against process-induced charging | David Michael Rogers, Mimi Qian, Kwadwo Appiah, Mark Randolph, Michael VanBuskirk +3 more | 2013-05-21 |
| 7972948 | Method for forming bit lines for semiconductor devices | Weidong Qian, Mark T. Ramsbey | 2011-07-05 |
| 7811915 | Method for forming bit lines for semiconductor devices | Weidong Qian, Mark T. Ramsbey | 2010-10-12 |
| 7297592 | Semiconductor memory with data retention liner | Minh Van Ngo, Arvind Halliyal, Hidehiko Shiraiwa, Rinji Sugino, Dawn Hopper +1 more | 2007-11-20 |
| 7176113 | LDC implant for mirrorbit to improve Vt roll-off and form sharper junction | Nga-Ching Wong, Weidong Qian, Sameer Haddad, Mark Randolph, Mark T. Ramsbey | 2007-02-13 |
| 7163860 | Method of formation of gate stack spacer and charge storage materials having reduced hydrogen content in charge trapping dielectric flash memory device | Yun Wu, Mark T. Ramsbey, Jean Y. Yang, Arvind Halliyal, Rinji Sugino +2 more | 2007-01-16 |
| 7060554 | PECVD silicon-rich oxide layer for reduced UV charging | Minh Van Ngo, Mark T. Ramsbey, Pei-Yuan Gao | 2006-06-13 |
| 7053446 | Memory wordline spacer | Kashmir Sahota, Mark T. Ramsbey | 2006-05-30 |
| 7033957 | ONO fabrication process for increasing oxygen content at bottom oxide-substrate interface in flash memory devices | Hidehiko Shiraiwa, Mark T. Ramsbey, Inkuk Kang, Jaeyong Park, Rinji Sugino +4 more | 2006-04-25 |
| 7023046 | Undoped oxide liner/BPSG for improved data retention | Minh Van Ngo, Angela T. Hui, Ning Cheng, Jeyong Park, Jean Y. Yang +3 more | 2006-04-04 |
| 7018868 | Disposable hard mask for memory bitline scaling | Jean Y. Yang, Jeff P. Erhardt, Cyrus E. Tabery, Weidong Qian, Mark T. Ramsbey +1 more | 2006-03-28 |
| 7018896 | UV-blocking layer for reducing UV-induced charging of SONOS dual-bit flash memory devices in BEOL processing | Minh Van Ngo, Mark T. Ramsbey, Arvind Halliyal, Jaeyong Park, Ning Cheng +6 more | 2006-03-28 |
| 6995423 | Memory device having a P+ gate and thin bottom oxide and method of erasing same | Wei Zheng, Chi Chang | 2006-02-07 |
| 6969886 | ONO fabrication process for reducing oxygen vacancy content in bottom oxide layer in flash memory devices | Jaeyong Park, Hidehiko Shiraiwa, Arvind Halliyal, Jean Y. Yang, Inkuk Kang +1 more | 2005-11-29 |
| 6962849 | Hard mask spacer for sublithographic bitline | Weidong Qian, Kouros Ghandehari, Taraneh Jamali-Beh, Mark T. Ramsbey, Ashok M. Khathuria | 2005-11-08 |
| 6958511 | Flash memory device and method of fabrication thereof including a bottom oxide layer with two regions with different concentrations of nitrogen | Arvind Halliyal, Amir H. Jafarpour, Hidehiko Shiraiwa, Mark T. Ramsbey, Jaeyong Park | 2005-10-25 |
| 6955965 | Process for fabrication of nitride layer with reduced hydrogen content in ONO structure in semiconductor device | Arvind Halliyal, Hidehiko Shiraiwa, Jean Y. Yang | 2005-10-18 |
| 6949481 | Process for fabrication of spacer layer with reduced hydrogen content in semiconductor device | Arvind Halliyal, Fred Cheung, Rinji Sugino, Hidehiko Shiraiwa, Jean Y. Yang | 2005-09-27 |
| 6927145 | Bitline hard mask spacer flow for memory cell scaling | Jean Y. Yang, Mark T. Ramsbey, Jaeyong Park, Emmanuil H. Lingunis | 2005-08-09 |
| 6912163 | Memory device having high work function gate and method of erasing same | Wei Zheng, Yun Wu, Hidehiko Shiraiwa, Mark T. Ramsbey | 2005-06-28 |
| 6884681 | Method of manufacturing a semiconductor memory with deuterated materials | Arvind Halliyal, Minh Van Ngo, Mark T. Ramsbey, Jean Y. Yang, Hidehiko Shiraiwa +1 more | 2005-04-26 |
| 6885590 | Memory device having A P+ gate and thin bottom oxide and method of erasing same | Wei Zheng, Chi Chang | 2005-04-26 |
| 6872609 | Narrow bitline using Safier for mirrorbit | Weidong Qian, Kouros Ghandehari, Taraneh Jamali-Beh | 2005-03-29 |