Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
TK

Tazrien Kamal — 42 Patents

AMD: 24 patents #445 of 9,280Top 5%
FAFasl: 9 patents #3 of 52Top 6%
Fujitsu Limited: 7 patents #4,529 of 24,456Top 20%
SLSpansion Llc.: 7 patents #128 of 769Top 20%
Cypress Semiconductor: 1 patents #1,454 of 1,866Top 80%
GRGeorgia Tech Research: 1 patents #1,150 of 2,755Top 45%
San Jose, CA: #1,306 of 32,062 inventorsTop 5%
California: #10,667 of 386,348 inventorsTop 3%
Overall (All Time): #72,062 of 4,157,543Top 2%
42 Patents All Time
Tazrien Kamal has been granted 42 US patents while listed as an inventor at AMD. The first was granted in 2002 and the most recent in April 2016. Tazrien Kamal ranks #72,062 of 4,157,543 US inventors in our database (top 1.7%). Patent records list Tazrien Kamal in San Jose, CA, US.

Patents per Year

Patents granted per year, 2002 to 2016Bar chart with a peak of 11 patents in 2005.peak 112002: 2 patents20022003: 6 patents2004: 8 patents20042005: 11 patents2006: 7 patents20062007: 3 patents2010: 1 patents20102011: 1 patents2013: 1 patents20132014: 1 patents2016: 1 patents2016

Issued Patents All Time

Showing 1–25 of 42 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
9318373 Method and apparatus for protection against process-induced charging David Michael Rogers, Mimi Qian, Kwadwo Appiah, Mark Randolph, Michael VanBuskirk +3 more 2016-04-19 $2,645,000
8673716 Memory manufacturing process with bitline isolation Mark T. Ramsbey, Jean Y. Yang, Emmanuil Lingunis, Hidehiko Shiraiwa, Yu Sun 2014-03-18 $3,810,000
8445966 Method and apparatus for protection against process-induced charging David Michael Rogers, Mimi Qian, Kwadwo Appiah, Mark Randolph, Michael VanBuskirk +3 more 2013-05-21 $1,207,000
7972948 Method for forming bit lines for semiconductor devices Weidong Qian, Mark T. Ramsbey 2011-07-05 $8,670,000
7811915 Method for forming bit lines for semiconductor devices Weidong Qian, Mark T. Ramsbey 2010-10-12 $2,619,000
7297592 Semiconductor memory with data retention liner Minh Van Ngo, Arvind Halliyal, Hidehiko Shiraiwa, Rinji Sugino, Dawn Hopper +1 more 2007-11-20 $6,431,000
7176113 LDC implant for mirrorbit to improve Vt roll-off and form sharper junction Nga-Ching Wong, Weidong Qian, Sameer Haddad, Mark Randolph, Mark T. Ramsbey 2007-02-13 $15,804,000
7163860 Method of formation of gate stack spacer and charge storage materials having reduced hydrogen content in charge trapping dielectric flash memory device Yun Wu, Mark T. Ramsbey, Jean Y. Yang, Arvind Halliyal, Rinji Sugino +2 more 2007-01-16 $6,080,000
7060554 PECVD silicon-rich oxide layer for reduced UV charging Minh Van Ngo, Mark T. Ramsbey, Pei-Yuan Gao 2006-06-13 $11,852,000
7053446 Memory wordline spacer Kashmir Sahota, Mark T. Ramsbey 2006-05-30 $15,789,000
7033957 ONO fabrication process for increasing oxygen content at bottom oxide-substrate interface in flash memory devices Hidehiko Shiraiwa, Mark T. Ramsbey, Inkuk Kang, Jaeyong Park, Rinji Sugino +4 more 2006-04-25
7023046 Undoped oxide liner/BPSG for improved data retention Minh Van Ngo, Angela T. Hui, Ning Cheng, Jeyong Park, Jean Y. Yang +3 more 2006-04-04 $14,413,000
7018868 Disposable hard mask for memory bitline scaling Jean Y. Yang, Jeff P. Erhardt, Cyrus E. Tabery, Weidong Qian, Mark T. Ramsbey +1 more 2006-03-28 $11,294,000
7018896 UV-blocking layer for reducing UV-induced charging of SONOS dual-bit flash memory devices in BEOL processing Minh Van Ngo, Mark T. Ramsbey, Arvind Halliyal, Jaeyong Park, Ning Cheng +6 more 2006-03-28 $11,294,000
6995423 Memory device having a P+ gate and thin bottom oxide and method of erasing same Wei Zheng, Chi Chang 2006-02-07 $12,481,000
6969886 ONO fabrication process for reducing oxygen vacancy content in bottom oxide layer in flash memory devices Jaeyong Park, Hidehiko Shiraiwa, Arvind Halliyal, Jean Y. Yang, Inkuk Kang +1 more 2005-11-29
6962849 Hard mask spacer for sublithographic bitline Weidong Qian, Kouros Ghandehari, Taraneh Jamali-Beh, Mark T. Ramsbey, Ashok M. Khathuria 2005-11-08 $6,799,000
6958511 Flash memory device and method of fabrication thereof including a bottom oxide layer with two regions with different concentrations of nitrogen Arvind Halliyal, Amir H. Jafarpour, Hidehiko Shiraiwa, Mark T. Ramsbey, Jaeyong Park 2005-10-25
6955965 Process for fabrication of nitride layer with reduced hydrogen content in ONO structure in semiconductor device Arvind Halliyal, Hidehiko Shiraiwa, Jean Y. Yang 2005-10-18
6949481 Process for fabrication of spacer layer with reduced hydrogen content in semiconductor device Arvind Halliyal, Fred Cheung, Rinji Sugino, Hidehiko Shiraiwa, Jean Y. Yang 2005-09-27
6927145 Bitline hard mask spacer flow for memory cell scaling Jean Y. Yang, Mark T. Ramsbey, Jaeyong Park, Emmanuil H. Lingunis 2005-08-09 $9,550,000
6912163 Memory device having high work function gate and method of erasing same Wei Zheng, Yun Wu, Hidehiko Shiraiwa, Mark T. Ramsbey 2005-06-28
6884681 Method of manufacturing a semiconductor memory with deuterated materials Arvind Halliyal, Minh Van Ngo, Mark T. Ramsbey, Jean Y. Yang, Hidehiko Shiraiwa +1 more 2005-04-26
6885590 Memory device having A P+ gate and thin bottom oxide and method of erasing same Wei Zheng, Chi Chang 2005-04-26 $7,241,000
6872609 Narrow bitline using Safier for mirrorbit Weidong Qian, Kouros Ghandehari, Taraneh Jamali-Beh 2005-03-29 $4,814,000