Issued Patents All Time
Showing 1–25 of 74 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11183509 | Non-volatile memory with silicided bit line contacts | Ching-Huang Lu, Simon S. Chan, Lei Xue | 2021-11-23 |
| 10692877 | Non-volatile memory with silicided bit line contacts | Ching-Huang Lu, Simon S. Chan, Lei Xue | 2020-06-23 |
| 10622370 | System and method for manufacturing self-aligned STI with single poly | Tim Thurgate, Shenqing Fang, Kuo-Tung Chang, Youseok Suh, Meng Ding +5 more | 2020-04-14 |
| 9666591 | Non-volatile memory with silicided bit line contacts | Ching-Huang Lu, Simon S. Chan, Lei Xue | 2017-05-30 |
| 9431503 | Integrating transistors with different poly-silicon heights on the same die | Chuan Lin, Bradley Marc Davis, Lei Xue, Simon S. Chan, Kenichi Ohtsuka +2 more | 2016-08-30 |
| 9276007 | System and method for manufacturing self-aligned STI with single poly | Tim Thurgate, Shenqing Fang, Kuo-Tung Chang, Youseok Suh, Meng Ding +5 more | 2016-03-01 |
| 9252154 | Non-volatile memory with silicided bit line contacts | Ching-Huang Lu, Simon S. Chan, Lei Xue | 2016-02-02 |
| 9196624 | Leakage reducing writeline charge protection circuit | Bradley Marc Davis, Mark Randolph, Sung-Yong Chung | 2015-11-24 |
| 9111985 | Shallow bipolar junction transistor | Alok Nandini Roy, Gulzar Kathawala, Zubin Patel | 2015-08-18 |
| 8866213 | Non-Volatile memory with silicided bit line contacts | Ching-Huang Lu, Simon S. Chan, Lei Xue | 2014-10-21 |
| 8809936 | Memory cell system with multiple nitride layers | Lei Xue, Rinji Sugino, Youseok Suh, Meng Ding, Shenqing Fang +1 more | 2014-08-19 |
| 8673716 | Memory manufacturing process with bitline isolation | Mark T. Ramsbey, Tazrien Kamal, Jean Y. Yang, Emmanuil Lingunis, Yu Sun | 2014-03-18 |
| 8652907 | Integrating transistors with different poly-silicon heights on the same die | Chuan Lin, Bradley Marc Davis, Lei Xue, Simon S. Chan, Kenichi Ohtsuka +2 more | 2014-02-18 |
| 8642441 | Self-aligned STI with single poly for manufacturing a flash memory device | Tim Thurgate, Shenqing Fang, Kuo-Tung Chang, Youseok Suh, Meng Ding +5 more | 2014-02-04 |
| 8598005 | Method and manufacture for embedded flash to achieve high quality spacers for core and high voltage devices and low temperature spacers for high performance logic devices | Simon S. Chan, Chuan Lin, Lei Xue, Kenichi Ohtsuka, Angela T. Hui | 2013-12-03 |
| 8143661 | Memory cell system with charge trap | Shenqing Fang, Rinji Sugino, Jayendra D. Bhakta, Takashi Orimoto, Hiroyuki Nansei +8 more | 2012-03-27 |
| 8119477 | Memory system with protection layer to cover the memory gate stack and methods for forming same | Youseok Suh, Harpreet Sachar, Satoshi Torii | 2012-02-21 |
| 8114736 | Integrated circuit system with memory system | Simon S. Chan, Kuo-Tung Chang, Angela T. Hui | 2012-02-14 |
| 7855114 | High K stack for non-volatile memory | Wei Zheng, Mark Randolph | 2010-12-21 |
| 7692236 | Multiple dual bit memory integrated circuit system | Michael Brennan, Jaeyong Park, Satoshi Torii | 2010-04-06 |
| 7675104 | Integrated circuit memory system employing silicon rich layers | Amol Joshi, Harpreet Sachar, Youseok Suh, Shenqing Fang, Chih-Yuh Yang +6 more | 2010-03-09 |
| 7501677 | SONOS memory with inversion bit-lines | Jaeyong Park, Satoshi Torii, Hideki Arakawa, Masaru Yano | 2009-03-10 |
| 7492001 | High K stack for non-volatile memory | Wei Zheng, Mark Randolph | 2009-02-17 |
| 7446369 | SONOS memory cell having high-K dielectric | Takashi Orimoto, Joong S. Jeon, Simon S. Chan, Harpreet Sachar | 2008-11-04 |
| 7416940 | Methods for fabricating flash memory devices | Satoshi Torii, Youseok Suh, Lei Xue | 2008-08-26 |