Issued Patents All Time
Showing 25 most recent of 100 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9922833 | Charge trapping split gate embedded flash memory and associated methods | Mark T. Ramsbey, Chun Chen, Sameer Haddad, Kuo-Tung Chang, Unsoon Kim +2 more | 2018-03-20 |
| 9466489 | Process for forming edge wordline implants adjacent edge wordlines | Tim Thurgate, Chun Chen | 2016-10-11 |
| 9461151 | Dual storage node memory | Fred Cheung, Hiroyuki Kinoshita, Chungho Lee, Chi Chang | 2016-10-04 |
| 8673716 | Memory manufacturing process with bitline isolation | Mark T. Ramsbey, Tazrien Kamal, Jean Y. Yang, Emmanuil Lingunis, Hidehiko Shiraiwa | 2014-03-18 |
| 8564042 | Dual storage node memory | Fred Cheung, Hiroyuki Kinoshita, Chungho Lee, Chi Chang | 2013-10-22 |
| 7995386 | Applying negative gate voltage to wordlines adjacent to wordline associated with read or verify to reduce adjacent wordline disturb | Yuji Mizuguchi, Mark Randolph, Darlene Hamilton, Yi He, Zhizheng Liu +9 more | 2011-08-09 |
| 7977218 | Thin oxide dummy tiling as charge protection | Cinti X. Chen, Yi He, Wenmei Li, Zhizheng Liu, Ming Sang Kwan +1 more | 2011-07-12 |
| 7759745 | Semiconductor memory device | Hideki Komori, Hisayuki Shimada, Hiroyuki Kinoshita | 2010-07-20 |
| 7632749 | Semiconductor device having a pad metal layer and a lower metal layer that are electrically coupled, whereas apertures are formed in the lower metal layer below a center area of the pad metal layer | Hiroyuki Ogawa, Yider Wu, Nian Yang, Kuo-Tung Chang | 2009-12-15 |
| 7482226 | Semiconductor memory device | Hideki Komori, Hisayuki Shimada, Hiroyuki Kinoshita | 2009-01-27 |
| 7439141 | Shallow trench isolation approach for improved STI corner rounding | Unsoon Kim, Hiroyuki Kinoshita, Kuo-Tung Chang, Harpreet Sachar, Mark S. Chang | 2008-10-21 |
| 7432178 | Bit line implant | Angela T. Hui, Jean Y. Yang, Mark T. Ramsbey, Weidong Qian | 2008-10-07 |
| 7323726 | Method and apparatus for coupling to a common line in an array | Kuo-Tung Chang | 2008-01-29 |
| 7307002 | Non-critical complementary masking method for poly-1 definition in flash memory device fabrication | Unsoon Kim, Hiroyuki Kinoshita, Krishnashree Achuthan, Christopher H. Raeder, Christopher Foster +2 more | 2007-12-11 |
| 7303964 | Self-aligned STI SONOS | Hidehiko Shiraiwa, Mark Randolph | 2007-12-04 |
| 7301193 | Structure and method for low Vss resistance and reduced DIBL in a floating gate memory cell | Shenqing Fang, Timothy Thurgate, Kuo-Tung Chang, Richard Fastow, Angela T. Hui +4 more | 2007-11-27 |
| 7226839 | Method and system for improving the topography of a memory array | King Wai Kelwin Ko, Hiroyuki Kinoshita, Hiroyuki Ogawa | 2007-06-05 |
| 7202540 | Semiconductor memory device | Hideki Komori, Hisayuki Shimada, Hiroyuki Kinoshita | 2007-04-10 |
| 7151027 | Method and device for reducing interface area of a memory device | Hiroyuki Ogawa, Yider Wu, Kuo-Tung Chang | 2006-12-19 |
| 7078314 | Memory device having improved periphery and core isolation | Unsoon Kim, Hiroyuki Kinoshita | 2006-07-18 |
| 7060564 | Memory device and method of simultaneous fabrication of core and periphery of same | Inkuk Kang, Hiroyuki Kinoshita, Weidong Qian, Kelwin Ko | 2006-06-13 |
| 7012008 | Dual spacer process for non-volatile memory devices | Jeffrey A. Shields, Tuan Pham, Mark T. Ramsbey, Angela T. Hui, Maria C. Chan | 2006-03-14 |
| 6995437 | Semiconductor device with core and periphery regions | Hiroyuki Kinoshita, Basab Banerjee, Christopher Foster, John R. Behnke, Cyrus E. Tabery | 2006-02-07 |
| 6989319 | Methods for forming nitrogen-rich regions in non-volatile semiconductor memory devices | Mark T. Ramsbey, Sameer Haddad, Vei-Han Chan, Chi Chang | 2006-01-24 |
| 6974995 | Method and system for forming dual gate structures in a nonvolatile memory using a protective layer | Angela T. Hui, Shenqing Fang, Hiroyuki Kinoshita, Kelwin Ko, Wenmei Li +2 more | 2005-12-13 |