Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
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Yu Sun — 100 Patents

AMD: 81 patents #48 of 9,280Top 1%
SLSpansion Llc.: 18 patents #27 of 769Top 4%
Fujitsu Limited: 12 patents #2,592 of 24,456Top 15%
Cypress Semiconductor: 2 patents #733 of 1,852Top 40%
FLFujitsu Semiconductor Limited: 1 patents #612 of 1,301Top 50%
FLFujitsu Amd Semiconductor Limited: 1 patents #14 of 40Top 35%
CSCyress Semiconductor: 1 patents #1 of 14Top 8%
Saratoga, CA: #59 of 2,933 inventorsTop 3%
California: #2,278 of 386,348 inventorsTop 1%
Overall (All Time): #14,510 of 4,157,543Top 1%
100 Patents All Time
Yu Sun has been granted 100 US patents while listed as an inventor at AMD. The first was granted in 1995 and the most recent in March 2018. Yu Sun ranks #14,510 of 4,157,543 US inventors in our database (top 0.35%). Patent records list Yu Sun in Saratoga, CA, US.

Issued Patents All Time

Showing 1–25 of 100 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
9922833 Charge trapping split gate embedded flash memory and associated methods Mark T. Ramsbey, Chun Chen, Sameer Haddad, Kuo-Tung Chang, Unsoon Kim +2 more 2018-03-20 $14,461,000
9466489 Process for forming edge wordline implants adjacent edge wordlines Tim Thurgate, Chun Chen 2016-10-11 $5,640,000
9461151 Dual storage node memory Fred Cheung, Hiroyuki Kinoshita, Chungho Lee, Chi Chang 2016-10-04 $6,131,000
8673716 Memory manufacturing process with bitline isolation Mark T. Ramsbey, Tazrien Kamal, Jean Y. Yang, Emmanuil Lingunis, Hidehiko Shiraiwa 2014-03-18 $3,810,000
8564042 Dual storage node memory Fred Cheung, Hiroyuki Kinoshita, Chungho Lee, Chi Chang 2013-10-22 $2,568,000
7995386 Applying negative gate voltage to wordlines adjacent to wordline associated with read or verify to reduce adjacent wordline disturb Yuji Mizuguchi, Mark Randolph, Darlene Hamilton, Yi He, Zhizheng Liu +9 more 2011-08-09 $1,938,000
7977218 Thin oxide dummy tiling as charge protection Cinti X. Chen, Yi He, Wenmei Li, Zhizheng Liu, Ming Sang Kwan +1 more 2011-07-12 $1,106,000
7759745 Semiconductor memory device Hideki Komori, Hisayuki Shimada, Hiroyuki Kinoshita 2010-07-20
7632749 Semiconductor device having a pad metal layer and a lower metal layer that are electrically coupled, whereas apertures are formed in the lower metal layer below a center area of the pad metal layer Hiroyuki Ogawa, Yider Wu, Nian Yang, Kuo-Tung Chang 2009-12-15
7482226 Semiconductor memory device Hideki Komori, Hisayuki Shimada, Hiroyuki Kinoshita 2009-01-27
7439141 Shallow trench isolation approach for improved STI corner rounding Unsoon Kim, Hiroyuki Kinoshita, Kuo-Tung Chang, Harpreet Sachar, Mark S. Chang 2008-10-21 $1,390,000
7432178 Bit line implant Angela T. Hui, Jean Y. Yang, Mark T. Ramsbey, Weidong Qian 2008-10-07
7323726 Method and apparatus for coupling to a common line in an array Kuo-Tung Chang 2008-01-29 $1,444,000
7307002 Non-critical complementary masking method for poly-1 definition in flash memory device fabrication Unsoon Kim, Hiroyuki Kinoshita, Krishnashree Achuthan, Christopher H. Raeder, Christopher Foster +2 more 2007-12-11 $706,000
7303964 Self-aligned STI SONOS Hidehiko Shiraiwa, Mark Randolph 2007-12-04 $5,444,000
7301193 Structure and method for low Vss resistance and reduced DIBL in a floating gate memory cell Shenqing Fang, Timothy Thurgate, Kuo-Tung Chang, Richard Fastow, Angela T. Hui +4 more 2007-11-27 $6,734,000
7226839 Method and system for improving the topography of a memory array King Wai Kelwin Ko, Hiroyuki Kinoshita, Hiroyuki Ogawa 2007-06-05 $3,927,000
7202540 Semiconductor memory device Hideki Komori, Hisayuki Shimada, Hiroyuki Kinoshita 2007-04-10
7151027 Method and device for reducing interface area of a memory device Hiroyuki Ogawa, Yider Wu, Kuo-Tung Chang 2006-12-19 $3,490,000
7078314 Memory device having improved periphery and core isolation Unsoon Kim, Hiroyuki Kinoshita 2006-07-18 $7,111,000
7060564 Memory device and method of simultaneous fabrication of core and periphery of same Inkuk Kang, Hiroyuki Kinoshita, Weidong Qian, Kelwin Ko 2006-06-13 $11,852,000
7012008 Dual spacer process for non-volatile memory devices Jeffrey A. Shields, Tuan Pham, Mark T. Ramsbey, Angela T. Hui, Maria C. Chan 2006-03-14 $17,128,000
6995437 Semiconductor device with core and periphery regions Hiroyuki Kinoshita, Basab Banerjee, Christopher Foster, John R. Behnke, Cyrus E. Tabery 2006-02-07 $12,481,000
6989319 Methods for forming nitrogen-rich regions in non-volatile semiconductor memory devices Mark T. Ramsbey, Sameer Haddad, Vei-Han Chan, Chi Chang 2006-01-24 $11,964,000
6974995 Method and system for forming dual gate structures in a nonvolatile memory using a protective layer Angela T. Hui, Shenqing Fang, Hiroyuki Kinoshita, Kelwin Ko, Wenmei Li +2 more 2005-12-13 $8,414,000