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Semiconductor device with core and periphery regions |
Hiroyuki Kinoshita, Yu Sun, Basab Banerjee, Christopher Foster, Cyrus E. Tabery |
2006-02-07 |
| 6780708 |
METHOD OF FORMING CORE AND PERIPHERY GATES INCLUDING TWO CRITICAL MASKING STEPS TO FORM A HARD MASK IN A CORE REGION THAT INCLUDES A CRITICAL DIMENSION LESS THAN ACHIEVABLE AT A RESOLUTION LIMIT OF LITHOGRAPHY |
Hiroyuki Kinoshita, Yu Sun, Basab Banerjee, Christopher Foster, Cyrus E. Tabery |
2004-08-24 |
| 6409879 |
System for controlling transistor spacer width |
Anthony J. Toprac, Matthew A. Purdy |
2002-06-25 |
| 6245581 |
Method and apparatus for control of critical dimension using feedback etch control |
Douglas J. Bonser, Anthony J. Toprac, Matthew A. Purdy, James H. Hussey, Jr. |
2001-06-12 |
| 6133132 |
Method for controlling transistor spacer width |
Anthony J. Toprac, Matthew A. Purdy |
2000-10-17 |