YS

Yu Sun

AM AMD: 81 patents #48 of 9,279Top 1%
SL Spansion Llc.: 18 patents #27 of 769Top 4%
Fujitsu Limited: 12 patents #2,592 of 24,456Top 15%
Cypress Semiconductor: 2 patents #733 of 1,852Top 40%
FL Fujitsu Amd Semiconductor Limited: 1 patents #14 of 40Top 35%
CS Cyress Semiconductor: 1 patents #1 of 14Top 8%
FL Fujitsu Semiconductor Limited: 1 patents #612 of 1,301Top 50%
📍 Saratoga, CA: #59 of 2,933 inventorsTop 3%
🗺 California: #2,242 of 386,348 inventorsTop 1%
Overall (All Time): #14,582 of 4,157,543Top 1%
100
Patents All Time

Issued Patents All Time

Showing 26–50 of 100 patents

Patent #TitleCo-InventorsDate
6936515 Method for fabricating a memory device having reverse LDD Hiroyuki Ogawa, Angela T. Hui 2005-08-30
6927129 Narrow wide spacer Kuo-Tung Chang, Angela T. Hui, Shenqing Fang 2005-08-09
6900085 ESD implant following spacer deposition Mark T. Ramsbey, Michael Fliesler, Mark Randolph, Mimi Qian 2005-05-31
6808992 Method and system for tailoring core and periphery cells in a nonvolatile memory Kelwin Ko, Shenqing Fang, Angela T. Hui, Hiroyuki Kinoshita, Wenmei Li +1 more 2004-10-26
6808996 Method for protecting gate edges from charge gain/loss in semiconductor device Tuan Pham, Mark T. Ramsbey, Sameer Haddad, Angela T. Hui, Chi Chang 2004-10-26
6787840 Nitridated tunnel oxide barriers for flash memory technology circuitry Tuan Pham, Mark T. Ramsbey, Chi Chang 2004-09-07
6780708 METHOD OF FORMING CORE AND PERIPHERY GATES INCLUDING TWO CRITICAL MASKING STEPS TO FORM A HARD MASK IN A CORE REGION THAT INCLUDES A CRITICAL DIMENSION LESS THAN ACHIEVABLE AT A RESOLUTION LIMIT OF LITHOGRAPHY Hiroyuki Kinoshita, Basab Banerjee, Christopher Foster, John R. Behnke, Cyrus E. Tabery 2004-08-24
6737703 Memory array with buried bit lines Richard Fastow, Sameer Haddad 2004-05-18
6730564 Salicided gate for virtual ground arrays Mark T. Ramsbey, Chi Chang, Hidehiko Shiraiwa 2004-05-04
6727143 Method and system for reducing charge gain and charge loss when using an ARC layer in interlayer dielectric formation Angela T. Hui, Mark T. Ramsbey, David Matsumoto 2004-04-27
6680509 Nitride barrier layer for protection of ONO structure from top oxide loss in fabrication of SONOS flash memory Yider Wu, Jean Y. Yang, Mark T. Ramsbey, Emmanuel H. Lingunis 2004-01-20
6664191 Non self-aligned shallow trench isolation process with disposable space to define sub-lithographic poly space Unsoon Kim, Yider Wu, Michael K. Templeton, Angela T. Hui, Chi Chang 2003-12-16
6645801 Salicided gate for virtual ground arrays Mark T. Ramsbey, Chi Chang 2003-11-11
6630384 Method of fabricating double densed core gates in sonos flash memory Michael A. Van Buskirk, Mark T. Ramsbey 2003-10-07
6605511 Method of forming nitridated tunnel oxide barriers for flash memory technology circuitry and STI and LOCOS isolation Tuan Pham, Mark T. Ramsbey, Chi Chang 2003-08-12
6583009 Innovative narrow gate formation for floating gate flash technology Angela T. Hui, Kelwin Ko, Hiroyuki Kinoshita, Sameer Haddad 2003-06-24
6566194 Salicided gate for virtual ground arrays Mark T. Ramsbey, Chi Chang 2003-05-20
6566736 Die seal for semiconductor device moisture protection Hiroyuki Ogawa, Yider Wu 2003-05-20
6529412 Source side sensing scheme for virtual ground read of flash eprom array with adjacent bit precharge Pau-Ling Chen, Michael A. Van Buskirk 2003-03-04
6509604 Nitridation barriers for nitridated tunnel oxide for circuitry for flash technology and for LOCOS/STI isolation Tuan Pham, Mark T. Ramsbey, Chi Chang 2003-01-21
6509232 Formation of STI (shallow trench isolation) structures within core and periphery areas of flash memory device Unsoon Kim, Mark S. Chang, Yider Wu, Chi Chang, Angela T. Hui 2003-01-21
6509229 Method for forming self-aligned contacts using consumable spacers Fei Wang, Ramkumar Subramanian 2003-01-21
6482699 Method for forming self-aligned contacts and local interconnects using decoupled local interconnect process YongZhong Hu, Fei Wang, Wenge Yang, Ramkumar Subramanian 2002-11-19
6475847 Method for forming a semiconductor device with self-aligned contacts using a liner oxide layer Minh Van Ngo, Fei Wang, Mark T. Ramsbey, Chi Chang, Angela T. Hui +1 more 2002-11-05
6455373 Semiconductor device having gate edges protected from charge gain/loss Tuan Pham, Mark T. Ramsbey, Sameer Haddad, Angela T. Hui, Chi Chang 2002-09-24