Issued Patents All Time
Showing 25 most recent of 33 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12180086 | Method for improving conductivity and blue light filtering efficiency of transparent conducting oxide (TCO) | Xuqiang Liu, Gang Liu, Nana Li | 2024-12-31 |
| 7566181 | Controlling critical dimensions of structures formed on a wafer in semiconductor processing | Alan Nolet | 2009-07-28 |
| 7217652 | Method of forming highly conductive semiconductor structures via plasma etch | — | 2007-05-15 |
| 6878622 | Method for forming SAC using a dielectric as a BARC and FICD enlarger | Ramkumar Subramanian, Fei Wang, Lewis Shen | 2005-04-12 |
| 6645824 | Combined optical profilometry and projection microscopy of integrated circuit structures | Junwei Bao, Xinhui Niu, Nickhil Jakatdar, Yasuhiro Okumoto | 2003-11-11 |
| 6627526 | Method for fabricating a conductive structure for a semiconductor device | Bhanwar Singh | 2003-09-30 |
| 6596623 | Use of organic spin on materials as a stop-layer for local interconnect, contact and via layers | Ramkumar Subramanian | 2003-07-22 |
| 6534411 | Method of high density plasma metal etching | Lewis Shen | 2003-03-18 |
| 6515328 | Semiconductor devices with reduced control gate dimensions | Lewis Shen, Mark S. Chang | 2003-02-04 |
| 6482699 | Method for forming self-aligned contacts and local interconnects using decoupled local interconnect process | YongZhong Hu, Fei Wang, Yu Sun, Ramkumar Subramanian | 2002-11-19 |
| 6452225 | Method and structure of etching a memory cell polysilicon gate layer using resist mask and etched silicon oxynitride | Lewis Shen | 2002-09-17 |
| 6423612 | Method of fabricating a shallow trench isolation structure with reduced topography | John Jianshi Wang, Fei Wang | 2002-07-23 |
| 6420240 | Method for reducing the step height of shallow trench isolation structures | John Jianshi Wang, Hao Fang | 2002-07-16 |
| 6416933 | Method to produce small space pattern using plasma polymerization layer | Bhanwar Singh, Bharath Rangarajan | 2002-07-09 |
| 6383939 | Method for etching memory gate stack using thin resist layer | Lewis Shen | 2002-05-07 |
| 6376389 | Method for eliminating anti-reflective coating in semiconductors | Ramkumar Subramanian, Minh Van Ngo, Kashmir Sahota, YongZhong Hu, Hiroyuki Kinoshita +1 more | 2002-04-23 |
| 6372651 | Method for trimming a photoresist pattern line for memory gate etching | Lewis Shen | 2002-04-16 |
| 6365509 | Semiconductor manufacturing method using a dielectric photomask | Ramkumar Subramanian, Marina V. Plat, Lewis Shen | 2002-04-02 |
| 6359307 | Method for forming self-aligned contacts and interconnection lines using dual damascene techniques | Fei Wang, Hiroyuki Kinoshita, Kashmir Sahota, Yu Sun | 2002-03-19 |
| 6348406 | Method for using a low dielectric constant layer as a semiconductor anti-reflective coating | Ramkumar Subramanian, Minh Van Ngo, Kashmir Sahota, YongZhong Hu, Hiroyuki Kinoshita +1 more | 2002-02-19 |
| 6306713 | Method for forming self-aligned contacts and local interconnects for salicided gates using a secondary spacer | YongZhong Hu, Fei Wang, Yu Sun, Hiroyuki Kinoshita | 2001-10-23 |
| 6291296 | Method for removing anti-reflective coating layer using plasma etch process before contact CMP | Angela T. Hui, Kashmir Sahota, Mark T. Ramsbey, Suzette K. Pangrle, Minh Van Ngo | 2001-09-18 |
| 6271154 | Methods for treating a deep-UV resist mask prior to gate formation etch to improve gate profile | Lewis Shen | 2001-08-07 |
| 6218310 | RTA methods for treating a deep-UV resist mask prior to gate formation etch to improve gate profile | Lewis Shen | 2001-04-17 |
| 6207575 | Local interconnect etch characterization using AFM | Bhanwar Sinjh | 2001-03-27 |