Issued Patents All Time
Showing 1–25 of 26 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10629474 | Integrated isolation capacitance structure | — | 2020-04-21 |
| 10008598 | Top drain LDMOS | Shekar Mallikarjunaswamy, John Chen | 2018-06-26 |
| 9337329 | Method of fabrication and device configuration of asymmetrical DMOSFET with schottky barrier source | Sung-Shan Tai | 2016-05-10 |
| 9159828 | Top drain LDMOS | Shekar Mallikarjunaswamy, John Chen | 2015-10-13 |
| 8835251 | Formation of high sheet resistance resistors and high capacitance capacitors by a single polysilicon process | Sung-Shan Tai | 2014-09-16 |
| 8524558 | Split gate with different gate materials and work functions to reduce gate resistance of ultra high density MOSFET | Sung-Shan Tai | 2013-09-03 |
| 8236653 | Configuration and method to form MOSFET devices with low resistance silicide gate and mesa contact regions | Sung-Shan Tai | 2012-08-07 |
| 8105905 | Configuration and method to form MOSFET devices with low resistance silicide gate and mesa contact regions | Sung-Shan Tai | 2012-01-31 |
| 8058687 | Split gate with different gate materials and work functions to reduce gate resistance of ultra high density MOSFET | Sung-Shan Tai | 2011-11-15 |
| 8022482 | Device configuration of asymmetrical DMOSFET with schottky barrier source | Sung-Shan Tai | 2011-09-20 |
| 7855422 | Formation of high sheet resistance resistors and high capacitance capacitors by a single polysilicon process | Sung-Shan Tai | 2010-12-21 |
| 7829941 | Configuration and method to form MOSFET devices with low resistance silicide gate and mesa contact regions | Sung-Shan Tai | 2010-11-09 |
| 7824977 | Completely decoupled high voltage and low voltage transistor manufacturing processes | Sung-Shan Tai | 2010-11-02 |
| 7805687 | One-time programmable (OTP) memory cell | Yu-Cheng Chang, Sung-Shan Tai | 2010-09-28 |
| 7256446 | One time programmable memory cell | Sung-Shan Tai | 2007-08-14 |
| 6842372 | EEPROM cell having a floating-gate transistor within a cell well and a process for fabricating the memory cell | — | 2005-01-11 |
| 6797568 | Flash technology transistors and methods for forming the same | — | 2004-09-28 |
| 6794236 | Eeprom device with improved capacitive coupling and fabrication process | — | 2004-09-21 |
| 6693830 | Single-poly two-transistor EEPROM cell with differentially doped floating gate | Jein-Chen Young | 2004-02-17 |
| 6627947 | Compact single-poly two transistor EEPROM cell | Jein-Chen Young, Stewart Logie | 2003-09-30 |
| 6506683 | In-situ process for fabricating a semiconductor device with integral removal of antireflection and etch stop layers | Angela T. Hui | 2003-01-14 |
| 6482699 | Method for forming self-aligned contacts and local interconnects using decoupled local interconnect process | Fei Wang, Wenge Yang, Yu Sun, Ramkumar Subramanian | 2002-11-19 |
| 6376389 | Method for eliminating anti-reflective coating in semiconductors | Ramkumar Subramanian, Minh Van Ngo, Kashmir Sahota, Hiroyuki Kinoshita, Fei Wang +1 more | 2002-04-23 |
| 6348406 | Method for using a low dielectric constant layer as a semiconductor anti-reflective coating | Ramkumar Subramanian, Minh Van Ngo, Kashmir Sahota, Hiroyuki Kinoshita, Fei Wang +1 more | 2002-02-19 |
| 6306713 | Method for forming self-aligned contacts and local interconnects for salicided gates using a secondary spacer | Fei Wang, Wenge Yang, Yu Sun, Hiroyuki Kinoshita | 2001-10-23 |