Issued Patents All Time
Showing 1–25 of 44 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10896968 | Device structure and manufacturing method using HDP deposited source-body implant block | Anup Bhalla, Francois Hebert, Sik Lui | 2021-01-19 |
| 9716156 | Device structure and manufacturing method using HDP deposited source-body implant block | Anup Bhalla, Francois Hebert, Sik Lui | 2017-07-25 |
| 9337329 | Method of fabrication and device configuration of asymmetrical DMOSFET with schottky barrier source | YongZhong Hu | 2016-05-10 |
| 9214545 | Dual gate oxide trench MOSFET with channel stop trench | Sik Lui, Xiaobin Wang | 2015-12-15 |
| 9024378 | Device structure and manufacturing method using HDP deposited source-body implant block | Anup Bhalla, Francois Hebert, Sik Lui | 2015-05-05 |
| 9006053 | Method of making MOSFET integrated with schottky diode with simplified one-time top-contact trench etching | Ji Pan, Daniel Ng, Anup Bhalla | 2015-04-14 |
| 9000514 | Fabrication of trench DMOS device having thick bottom shielding oxide | Yeeheng Lee, Hong Chang, John Chen | 2015-04-07 |
| 8907416 | Dual gate oxide trench MOSFET with channel stop trench | Sik Lui, Xiaobin Wang | 2014-12-09 |
| 8847306 | Direct contact in trench with three-mask shield gate process | Hamza Yilmaz, Anup Bhalla, Hong Chang, John Chen | 2014-09-30 |
| 8835251 | Formation of high sheet resistance resistors and high capacitance capacitors by a single polysilicon process | YongZhong Hu | 2014-09-16 |
| 8748268 | Method of making MOSFET integrated with schottky diode with simplified one-time top-contact trench etching | Ji Pan, Daniel Ng, Anup Bhalla | 2014-06-10 |
| 8709895 | Manufacturing method power semiconductor device | Hung-Sheng Tsai | 2014-04-29 |
| 8643094 | Method of forming a self-aligned contact opening in MOSFET | Teng-Hao Yeh, Chia-Hui Chen | 2014-02-04 |
| 8536646 | Trench type power transistor device | Teng-Hao Yeh, Shian-Hau Liao, Chia-Hui Chen | 2013-09-17 |
| 8524558 | Split gate with different gate materials and work functions to reduce gate resistance of ultra high density MOSFET | YongZhong Hu | 2013-09-03 |
| 8507362 | Process of forming ultra thin wafers having an edge support ring | Tao Feng | 2013-08-13 |
| 8471368 | Polysilicon control etch back indicator | Yu Wang, Tiesheng Li, Hong Chang | 2013-06-25 |
| 8394702 | Method for making dual gate oxide trench MOSFET with channel stop using three or four masks process | Sik Lui, Xiaobin Wang | 2013-03-12 |
| 8372708 | Device structure and manufacturing method using HDP deposited using deposited source-body implant block | Anup Bhalla, Francois Hebert, Sik Lui | 2013-02-12 |
| 8334566 | Semiconductor power device having shielding electrode for improving breakdown voltage | — | 2012-12-18 |
| 8252647 | Fabrication of trench DMOS device having thick bottom shielding oxide | Yeeheng Lee, Hong Chang, John Chen | 2012-08-28 |
| 8236653 | Configuration and method to form MOSFET devices with low resistance silicide gate and mesa contact regions | YongZhong Hu | 2012-08-07 |
| 8193061 | Polysilicon control etch-back indicator | Yu Wang, Tiesheng Li, Hong Chang | 2012-06-05 |
| 8187939 | Direct contact in trench with three-mask shield gate process | Hamza Yilmaz, Anup Bhalla, Hong Chang, John Chen | 2012-05-29 |
| 8105905 | Configuration and method to form MOSFET devices with low resistance silicide gate and mesa contact regions | YongZhong Hu | 2012-01-31 |