Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8271810 | Method and apparatus for dynamically detecting environmental conditions and adjusting drive strength in response to the detecting | David Lindley, Morgan Whately, Vinod Rajan, Muthukumar Nagarajan, Jun Li +1 more | 2012-09-18 |
| 7173851 | 3.5 transistor non-volatile memory cell using gate breakdown phenomena | John M. Callahan, Hemanshu T. Vernenker, Glen Arnold Rosendale, Harry Luan, Zhongshang Liu | 2007-02-06 |
| 7042772 | Methods and circuits for programming of a semiconductor memory cell and memory array using a breakdown phenomenon in an ultra-thin dielectric | Jianguo Wang, David Fong, Jack Peng, Fei Ye | 2006-05-09 |
| 7031209 | Methods and circuits for testing programmability of a semiconductor memory cell and memory array using a breakdown phenomenon in an ultra-thin dielectric | Jianguo Wang, David Fong, Jack Peng, Fei Ye | 2006-04-18 |
| 6972986 | Combination field programmable gate array allowing dynamic reprogrammability and non-votatile programmability based upon transistor gate oxide breakdown | Jack Peng, Zhongshan Liu, Fei Ye | 2005-12-06 |
| 6940751 | High density semiconductor memory cell and memory array using a single transistor and having variable gate oxide breakdown | Jack Peng | 2005-09-06 |
| 6900085 | ESD implant following spacer deposition | Mark T. Ramsbey, Mark Randolph, Mimi Qian, Yu Sun | 2005-05-31 |
| 6770938 | Diode fabrication for ESD/EOS protection | Mark T. Ramsbey, Mark Randolph, Ian Morgan, Timothy Thurgate, Paohua Kuo +1 more | 2004-08-03 |
| 6440789 | Photoresist spacer process simplification to eliminate the standard polysilicon or oxide spacer process for flash memory circuits | Darlene Hamilton, Len Toyoshiba | 2002-08-27 |
| 6395568 | Method and apparatus for achieving bond pad crater sensing and ESD protection integrated circuit products | Richard C. Blish, II, Colin Hatchard, Ian Morgan | 2002-05-28 |
| 6238975 | Method for improving electrostatic discharge (ESD) robustness | Mark Randolph | 2001-05-29 |
| 5642311 | Overerase correction for flash memory which limits overerase and prevents erase verify errors | Lee Cleveland, Chung K. Chang, Yuan Tang, Nancy Leong, Tiao-Hua Kuo | 1997-06-24 |