YS

Yu Sun

AM AMD: 81 patents #48 of 9,279Top 1%
SL Spansion Llc.: 18 patents #27 of 769Top 4%
Fujitsu Limited: 12 patents #2,592 of 24,456Top 15%
Cypress Semiconductor: 2 patents #733 of 1,852Top 40%
FL Fujitsu Amd Semiconductor Limited: 1 patents #14 of 40Top 35%
CS Cyress Semiconductor: 1 patents #1 of 14Top 8%
FL Fujitsu Semiconductor Limited: 1 patents #612 of 1,301Top 50%
📍 Saratoga, CA: #59 of 2,933 inventorsTop 3%
🗺 California: #2,242 of 386,348 inventorsTop 1%
Overall (All Time): #14,582 of 4,157,543Top 1%
100
Patents All Time

Issued Patents All Time

Showing 76–100 of 100 patents

Patent #TitleCo-InventorsDate
6160317 Method of spacer formation and source protection after self-aligned source formed and a device provided by such a method Chi Chang, Mark T. Ramsbey 2000-12-12
6133619 Reduction of silicon oxynitride film delamination in integrated circuit inter-level dielectrics Kashmir Sahota, Richard J. Huang, David Matsumoto, Mark T. Ramsbey, Judith Quan Rizzuto 2000-10-17
6124640 Scalable and reliable integrated circuit inter-level dielectric Kashmir Sahota, Richard J. Huang, Hung-Sheng Chen 2000-09-26
6124608 Non-volatile trench semiconductor device having a shallow drain region Yowjuang W. Liu, Donald L. Wollesen 2000-09-26
6040597 Isolation boundaries in flash memory cores Unsoon Kim, Yowjuang W. Liu 2000-03-21
6034394 Methods and arrangements for forming a floating gate in non-volatile memory semiconductor devices Mark T. Ramsbey, Tuan Pham, Kenneth Wo-Wai Au 2000-03-07
6004862 Core array and periphery isolation technique Unsoon Kim, Hung-Sheng Chen, Kashmir Sahota 1999-12-21
6002151 Non-volatile trench semiconductor device Yowjuang W. Liu, Donald L. Wollesen 1999-12-14
6001713 Methods for forming nitrogen-rich regions in a floating gate and interpoly dielectric layer in a non-volatile semiconductor memory device Mark T. Ramsbey, Vei-Han Chan, Sameer Haddad, Chi Chang, Raymond Yu 1999-12-14
5999452 Dual source side polysilicon select gate structure and programming method utilizing single tunnel oxide for NAND array flash memory Pau-Ling Chen, Mike Van Buskirk, Shane Hollmer, Binh Quang Le, Shoichi Kawamura +3 more 1999-12-07
5981364 Method of forming a silicon gate to produce silicon devices with improved performance Mark T. Ramsbey, Hsingya Arthur Wang 1999-11-09
5981341 Sidewall spacer for protecting tunnel oxide during isolation trench formation in self-aligned flash memory core Unsoon Kim, Yowjuang W. Liu, Angela T. Hui 1999-11-09
5972751 Methods and arrangements for introducing nitrogen into a tunnel oxide in a non-volatile semiconductor memory device Mark T. Ramsbey, Sameer Haddad, Vei-Han Chan, Chi Chang 1999-10-26
5966618 Method of forming dual field isolation structures Tuan Pham, Mark T. Ramsbey, Chi Chang 1999-10-12
5933730 Method of spacer formation and source protection after self-aligned source is formed and a device provided by such a method Chi Chang, Mark T. Ramsbey 1999-08-03
5925909 Three-dimensional complementary field effect transistor process and structures Yowjuang W. Liu 1999-07-20
5912489 Dual source side polysilicon select gate structure utilizing single tunnel oxide for NAND array flash memory Pau-Ling Chen, Mike Van Buskirk, Shane Hollmer, Binh Quang Le, Shoichi Kawamura +3 more 1999-06-15
5907781 Process for fabricating an integrated circuit with a self-aligned contact Hung-Sheng Chen, Unsoon Kim, Chi Chang, Mark T. Ramsbey, Mark Randolph +4 more 1999-05-25
5793677 Using floating gate devices as select gate devices for NAND flash memory and its bias scheme Chung-You Hu, Chi Chang, Sameer Haddad 1998-08-11
5747882 Device including means for preventing tungsten silicide lifting, and method of fabrication thereof Hsingya Arthur Wang, Mark T. Ramsbey 1998-05-05
5739063 High temperature local oxidation of silicon for fine line patterns Yowjuang W. Liu 1998-04-14
5672524 Three-dimensional complementary field effect transistor process Yowjuang W. Liu 1997-09-30
5612249 Post-gate LOCOS Yowjuang W. Liu 1997-03-18
5517443 Method and system for protecting a stacked gate edge in a semi-conductor device from self aligned source (SAS) etch in a semi-conductor device David Kuan-Yu Liu, Chi Chang 1996-05-14
5470773 Method protecting a stacked gate edge in a semiconductor device from self aligned source (SAS) etch David Kuan-Yu Liu, Chi Chang 1995-11-28