Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
HW

Hsingya Arthur Wang — 38 Patents

AMD: 17 patents #693 of 9,280Top 8%
SHSk Hynix: 10 patents #756 of 4,849Top 20%
HAHyundai Electronics America: 5 patents #16 of 148Top 15%
HAHynix Semiconductor America: 4 patents #1 of 5Top 20%
ISIntegrated Silicon Solution: 2 patents #26 of 80Top 35%
San Jose, CA: #1,502 of 32,062 inventorsTop 5%
California: #12,412 of 386,348 inventorsTop 4%
Overall (All Time): #84,675 of 4,157,543Top 3%
38 Patents All Time
Hsingya Arthur Wang has been granted 38 US patents while listed as an inventor at AMD. The first was granted in 1987 and the most recent in June 2024. Hsingya Arthur Wang ranks #84,675 of 4,157,543 US inventors in our database (top 2.0%). Patent records list Hsingya Arthur Wang in San Jose, CA, US.

Issued Patents All Time

Showing 1–25 of 38 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12021059 Wafer-bonding structure and method of forming thereof Sheng-Yuan CHOU, Yu-Ting Wang, Wan-Yi Chang 2024-06-25
11616145 FINFET stack gate memory and method of forming thereof 2023-03-28
8946003 Method of forming transistors with ultra-short gate feature Peter Rabkin, Kai-Cheng Chou 2015-02-03
8288219 Method of forming a non-volatile memory cell using off-set spacers Peter Rabkin, Kai-Cheng Chou 2012-10-16
7250341 Flash memory device having poly spacers Kai-Cheng Chou, Peter Rabkin 2007-07-31
7202134 Method of forming transistors with ultra-short gate feature Peter Rabkin, Kai-Cheng Chou 2007-04-10
7160774 Method of forming polysilicon layers in non-volatile memory Peter Rabkin, Kai-Cheng Chou 2007-01-09
7154141 Source side programming Yuan Tang, Haike Dong, Ming Sang Kwan, Peter Rabkin 2006-12-26
6911370 Flash memory device having poly spacers Kai-Cheng Chou, Peter Rabkin 2005-06-28
6876582 Flash memory cell erase scheme using both source and channel regions Kai-Cheng Chou, Peter Rabkin 2005-04-05
6849489 Method for forming transistors with ultra-short gate feature Peter Rabkin, Kai-Cheng Chou 2005-02-01
6818504 Processes and structures for self-aligned contact non-volatile memory with peripheral transistors easily modifiable for various technologies and applications Peter Rabkin, Kai-Cheng Chou 2004-11-16
6812515 Polysilicon layers structure and method of forming same Peter Rabkin, Kai-Cheng Chou 2004-11-02
6777741 Non-volatile memory cells with selectively formed floating gate Peter Rabkin, Kai-Cheng Chou 2004-08-17
6746906 Transistor with ultra-short gate feature and method of fabricating the same Peter Rabkin, Kai-Cheng Chou 2004-06-08
6559008 Non-volatile memory cells with selectively formed floating gate Peter Rabkin, Kai-Cheng Chou 2003-05-06
6509237 Flash memory cell fabrication sequence Peter Rabkin, Frank Qian 2003-01-21
6169693 Self-convergence of post-erase threshold voltages in a flash memory cell using transient response I-Chuin Peter Chan, Feng Qian 2001-01-02
6043123 Triple well flash memory fabrication process Jein-Chen Young, Ming Sang Kwan 2000-03-28
6026026 Self-convergence of post-erase threshold voltages in a flash memory cell using transient response I-Chuin Peter Chan, Feng Qian 2000-02-15
5989938 Method of fabricating topside structure of a semiconductor device Bandali B. Mohamed, Shyam Garg, Bruce Lynn Pickelsimer 1999-11-23 $2,771,000
5981364 Method of forming a silicon gate to produce silicon devices with improved performance Mark T. Ramsbey, Yu Sun 1999-11-09 $2,369,000
5920506 Method and apparatus for bulk preprogramming flash memory cells with minimal source and drain currents Haike Dong, Jein-Chen Young, Yuan Tang, Aaron Yip, Kenneth Miu 1999-07-06
5908318 Method of forming low capacitance interconnect structures on semiconductor substrates David Michael Rogers 1999-06-01 $4,882,000
5899726 Method of forming oxide isolation in a semiconductor device Mark T. Ramsbey, Jein-Chen Young 1999-05-04 $2,190,000