Shyam Garg — 16 Patents at AMD

Shyam Garg has been granted 16 US patents while listed as an inventor at AMD. The first was granted in 1985 and the most recent in October 2000. Shyam Garg ranks #284,196 of 4,157,543 US inventors in our database (top 6.8%). Patent records list Shyam Garg in Beaverton, OR, US.

Patents per Year

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Showing 1–16 of 16 patents

Patent #	Title	Co-Inventors	Date	Approx Value ⓘ
6140216	Post etch silicide formation using dielectric etchback after global planarization	Robert B. Richart	2000-10-31	$4,395,000
5989938	Method of fabricating topside structure of a semiconductor device	Hsingya Arthur Wang, Bandali B. Mohamed, Bruce Lynn Pickelsimer	1999-11-23	$2,771,000
5952246	Nitride selective, anisotropic Cl.sub.2 /He etch process	Fei Wang, Robert B. Rickart	1999-09-14	$3,488,000
5811334	Wafer cleaning procedure useful in the manufacture of a non-volatile memory device	James F. Buller, Basab Bandyopadhyay, Nipendra J. Patel, Thomas E. Spikes, Jr.	1998-09-22	$3,273,000
5774395	Electrically erasable reference cell for accurately determining threshold voltage of a non-volatile memory at a plurality of threshold voltage levels	Robert B. Richart	1998-06-30	$4,223,000
5728453	Method of fabricating topside structure of a semiconductor device	Hsingya Arthur Wang, Mohamed B. Bandali, Bruce Lynn Pickelsimer	1998-03-17	$13,043,000
5717632	Apparatus and method for multiple-level storage in non-volatile memories	Robert B. Richart	1998-02-10	$5,849,000
5632855	Thermal oxide etch technique	Stephen Alister Jones	1997-05-27	$15,117,000
5612253	Method for forming ordered titanium nitride and titanium silicide upon a semiconductor wafer using a three-step anneal process	M. M. Farahani	1997-03-18	$11,685,000
5581502	Method for reading a non-volatile memory array	Robert B. Richart, Nipendra J. Patel	1996-12-03	$4,546,000
5549786	Highly selective, highly uniform plasma etch process for spin-on glass	Stephen Alister Jones, James F. Buller, Miguel Santana, Jr.	1996-08-27	$4,675,000
5546340	Non-volatile memory array with over-erase correction	Chung-You Hu, Robert B. Richart, Sanjay Banerjee	1996-08-13	$3,236,000
5427963	Method of making a MOS device with drain side channel implant	Robert B. Richart, Bradley T. Moore	1995-06-27	$11,435,000
5376573	Method of making a flash EPROM device utilizing a single masking step for etching and implanting source regions within the EPROM core and redundancy areas	Robert B. Richart, Fei Wang	1994-12-27	$9,009,000
4536947	CMOS process for fabricating integrated circuits, particularly dynamic memory cells with storage capacitors	Mark Bohr, Ken K. Yu, Leo D. Yau	1985-08-27	$26,681,000
4505026	CMOS Process for fabricating integrated circuits, particularly dynamic memory cells	Mark Bohr, Ken K. Yu, Leo D. Yau	1985-03-19	$28,481,000

Shyam Garg — 16 Patents

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