Issued Patents All Time
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6140216 | Post etch silicide formation using dielectric etchback after global planarization | Robert B. Richart | 2000-10-31 |
| 5989938 | Method of fabricating topside structure of a semiconductor device | Hsingya Arthur Wang, Bandali B. Mohamed, Bruce Lynn Pickelsimer | 1999-11-23 |
| 5952246 | Nitride selective, anisotropic Cl.sub.2 /He etch process | Fei Wang, Robert B. Rickart | 1999-09-14 |
| 5811334 | Wafer cleaning procedure useful in the manufacture of a non-volatile memory device | James F. Buller, Basab Bandyopadhyay, Nipendra J. Patel, Thomas E. Spikes, Jr. | 1998-09-22 |
| 5774395 | Electrically erasable reference cell for accurately determining threshold voltage of a non-volatile memory at a plurality of threshold voltage levels | Robert B. Richart | 1998-06-30 |
| 5728453 | Method of fabricating topside structure of a semiconductor device | Hsingya Arthur Wang, Mohamed B. Bandali, Bruce Lynn Pickelsimer | 1998-03-17 |
| 5717632 | Apparatus and method for multiple-level storage in non-volatile memories | Robert B. Richart | 1998-02-10 |
| 5632855 | Thermal oxide etch technique | Stephen Alister Jones | 1997-05-27 |
| 5612253 | Method for forming ordered titanium nitride and titanium silicide upon a semiconductor wafer using a three-step anneal process | M. M. Farahani | 1997-03-18 |
| 5581502 | Method for reading a non-volatile memory array | Robert B. Richart, Nipendra J. Patel | 1996-12-03 |
| 5549786 | Highly selective, highly uniform plasma etch process for spin-on glass | Stephen Alister Jones, James F. Buller, Miguel Santana, Jr. | 1996-08-27 |
| 5546340 | Non-volatile memory array with over-erase correction | Chung-You Hu, Robert B. Richart, Sanjay Banerjee | 1996-08-13 |
| 5427963 | Method of making a MOS device with drain side channel implant | Robert B. Richart, Bradley T. Moore | 1995-06-27 |
| 5376573 | Method of making a flash EPROM device utilizing a single masking step for etching and implanting source regions within the EPROM core and redundancy areas | Robert B. Richart, Fei Wang | 1994-12-27 |
| 4536947 | CMOS process for fabricating integrated circuits, particularly dynamic memory cells with storage capacitors | Mark Bohr, Ken K. Yu, Leo D. Yau | 1985-08-27 |
| 4505026 | CMOS Process for fabricating integrated circuits, particularly dynamic memory cells | Mark Bohr, Ken K. Yu, Leo D. Yau | 1985-03-19 |