Issued Patents All Time
Showing 1–25 of 56 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6720227 | Method of forming source/drain regions in a semiconductor device | Daniel Kadosh, Jon D. Cheek, James F. Buller | 2004-04-13 |
| 6599810 | Shallow trench isolation formation with ion implantation | Nick Kepler, Olov Karlsson, Larry Wang, Effiong Ibok, Christopher F. Lyons | 2003-07-29 |
| 6380047 | Shallow trench isolation formation with two source/drain masks and simplified planarization mask | Nick Kepler, Olov Karlsson, Larry Wang, Effiong Ibok, Christopher F. Lyons | 2002-04-30 |
| 6376330 | Dielectric having an air gap formed between closely spaced interconnect lines | H. Jim Fulford, Robert Dawson, Fred N. Hause, Mark W. Michael, William S. Brennan | 2002-04-23 |
| 6353253 | Semiconductor isolation region bounded by a trench and covered with an oxide to improve planarization | Fred N. Hause, H. Jim Fulford, Robert Dawson, Mark W. Michael, William S. Brennan | 2002-03-05 |
| 6326298 | Substantially planar semiconductor topography using dielectrics and chemical mechanical polish | Robert Dawson, Mark W. Michael, H. Jim Fulford, Fred N. Hause, William S. Brennan | 2001-12-04 |
| 6309947 | Method of manufacturing a semiconductor device with improved isolation region to active region topography | Douglas J. Bonser | 2001-10-30 |
| 6208015 | Interlevel dielectric with air gaps to lessen capacitive coupling | H. Jim Fulford, Robert Dawson, Fred N. Hause, Mark W. Michael, William S. Brennan | 2001-03-27 |
| 6171962 | Shallow trench isolation formation without planarization mask | Olov Karlsson, Christopher F. Lyons, Nick Kepler, Larry Wang, Effiong Ibok | 2001-01-09 |
| 6165906 | Semiconductor topography employing a shallow trench isolation structure with an improved trench edge | Douglas J. Bonser, Michael J. McBride | 2000-12-26 |
| 6162699 | Method for generating limited isolation trench width structures and a device having a narrow isolation trench surrounding its periphery | Larry Wang, Nick Kepler, Olov Karlsson, Effiong Ibok, Christopher F. Lyons | 2000-12-19 |
| 6153833 | Integrated circuit having interconnect lines separated by a dielectric having a capping layer | Robert Dawson, Mark W. Michael, H. Jim Fulford, Fred N. Hause, William S. Brennan | 2000-11-28 |
| 6150721 | Integrated circuit which uses a damascene process for producing staggered interconnect lines | H. Jim Fulford, Robert Dawson, Fred N. Hause, Mark W. Michael, William S. Brennan | 2000-11-21 |
| 6143624 | Shallow trench isolation formation with spacer-assisted ion implantation | Nick Kepler, Olov Karlsson, Larry Wang, Effiong Ibok, Christopher F. Lyons | 2000-11-07 |
| 6130467 | Shallow trench isolation with spacers for improved gate oxide quality | Nick Kepler, Olov Karlsson, Larry Wang, Effiong Ibok, Christopher F. Lyons | 2000-10-10 |
| 6127719 | Subfield conductive layer and method of manufacture | H. Jim Fulford, Robert Dawson, Fred N. Hause, Mark W. Michael, William S. Brennan | 2000-10-03 |
| 6127264 | Integrated circuit having conductors of enhanced cross-sectional area | H. Jim Fulford, Robert Dawson, Fred N. Hause, Mark W. Michael, William S. Brennan | 2000-10-03 |
| 6124183 | Shallow trench isolation formation with simplified reverse planarization mask | Olov Karlsson, Christopher F. Lyons, Nick Kepler, Larry Wang, Effiong Ibok | 2000-09-26 |
| 6090712 | Shallow trench isolation formation with no polish stop | Christopher F. Lyons, Nick Kepler, Olov Karlsson, Larry Wang, Effiong Obok | 2000-07-18 |
| 6090703 | Method of forming an integrated circuit having conductors of enhanced cross-sectional area with etch stop barrier layer | H. Jim Fulford, William S. Brennan, Fred N. Hause, Robert Dawson, Mark W. Michael | 2000-07-18 |
| 6091149 | Dissolvable dielectric method and structure | Fred N. Hause, Robert Dawson, H. Jim Fulford, Mark W. Michael, William S. Brennan | 2000-07-18 |
| 6074927 | Shallow trench isolation formation with trench wall spacer | Nick Kepler, Olov Karlsson, Larry Wang, Effiong Ibok, Christopher F. Lyons | 2000-06-13 |
| 6049134 | Mask generation technique for producing an integrated circuit with optimal metal interconnect layout for achieving global planarization | Mark W. Michael, Robert Dawson, Fred N. Hause, H. Jim Fulford, William S. Brennan | 2000-04-11 |
| 6037671 | Stepper alignment mark structure for maintaining alignment integrity | Nick Kepler, Olov Karlsson, Larry Wang, Effiong Ibok, Christopher F. Lyons | 2000-03-14 |
| 6031289 | Integrated circuit which uses a recessed local conductor for producing staggered interconnect lines | H. Jim Fulford, Robert Dawson, Fred N. Hause, Mark W. Michael, William S. Brennan | 2000-02-29 |