Issued Patents All Time
Showing 25 most recent of 67 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9276008 | Embedded NVM in a HKMG process | Frank K. Baker, Jr. | 2016-03-01 |
| 9054220 | Embedded NVM in a HKMG process | Frank K. Baker, Jr. | 2015-06-09 |
| 7422956 | Semiconductor device and method of making semiconductor device comprising multiple stacked hybrid orientation layers | Andrew Waite | 2008-09-09 |
| 7410876 | Methodology to reduce SOI floating-body effect | Byoung W. Min, Venkat R. Kolagunta | 2008-08-12 |
| 7253484 | Low-power multiple-channel fully depleted quantum well CMOSFETs | James Pan, John G. Pellerin | 2007-08-07 |
| 7238990 | Interlayer dielectric under stress for an integrated circuit | James D. Burnett | 2007-07-03 |
| 7235433 | Silicon-on-insulator semiconductor device with silicon layers having different crystal orientations and method of forming the silicon-on-insulator semiconductor device | Andrew Waite | 2007-06-26 |
| 7208383 | Method of manufacturing a semiconductor component | Chad Weintraub, James F. Buller, Derick J. Wristers | 2007-04-24 |
| 7179745 | Method for offsetting a silicide process from a gate electrode of a semiconductor device | Andrew Waite, David E. Brown | 2007-02-20 |
| 7091106 | Method of reducing STI divot formation during semiconductor device fabrication | Douglas J. Bonser, Johannes Groschopf, Srikanteswara Dakshina-Murthy, John G. Pellerin | 2006-08-15 |
| 7074657 | Low-power multiple-channel fully depleted quantum well CMOSFETs | James Pan, John G. Pellerin | 2006-07-11 |
| 6833307 | Method for manufacturing a semiconductor component having an early halo implant | Derick J. Wristers, Chad Weintraub, James F. Buller | 2004-12-21 |
| 6787464 | Method of forming silicide layers over a plurality of semiconductor devices | Scott Luning | 2004-09-07 |
| 6720227 | Method of forming source/drain regions in a semiconductor device | Daniel Kadosh, James F. Buller, Basab Bandyopadhyay | 2004-04-13 |
| 6674135 | Semiconductor structure having elevated salicided source/drain regions and metal gate electrode on nitride/oxide dielectric | Derick J. Wristers, Mark I. Gardner | 2004-01-06 |
| 6638829 | Semiconductor structure having a metal gate electrode and elevated salicided source/drain regions and a method for manufacture | Derick J. Wristers, Mark I. Gardner | 2003-10-28 |
| 6580122 | Transistor device having an enhanced width dimension and a method of making same | Derick J. Wristers, John G. Pellerin | 2003-06-17 |
| 6566696 | Self-aligned VT implant | Mark W. Michael, Derick J. Wristers, James F. Buller | 2003-05-20 |
| 6541321 | Method of making transistors with gate insulation layers of differing thickness | James F. Buller | 2003-04-01 |
| 6506642 | Removable spacer technique | Scott Luning, Daniel Kadosh, James F. Buller, David E. Brown | 2003-01-14 |
| 6426262 | Method of analyzing the effects of shadowing of angled halo implants | Mark B. Fuselier, Frederick N. Hause, Marilyn I. Wright | 2002-07-30 |
| 6417539 | High density memory cell assembly and methods | Mark I. Gardner, Derick J. Wristers | 2002-07-09 |
| 6406964 | Method of controlling junction recesses in a semiconductor device | Derick J. Wristers, John G. Pellerin | 2002-06-18 |
| 6403979 | Test structure for measuring effective channel length of a transistor | Daniel Kadosh | 2002-06-11 |
| 6399493 | Method of silicide formation by silicon pretreatment | Robert Dawson, John G. Pellerin | 2002-06-04 |