| 9276008 |
Embedded NVM in a HKMG process |
Frank K. Baker, Jr. |
2016-03-01 |
|
| 9054220 |
Embedded NVM in a HKMG process |
Frank K. Baker, Jr. |
2015-06-09 |
$9,518,000 |
| 7422956 |
Semiconductor device and method of making semiconductor device comprising multiple stacked hybrid orientation layers |
Andrew Waite |
2008-09-09 |
$8,320,000 |
| 7410876 |
Methodology to reduce SOI floating-body effect |
Byoung W. Min, Venkat R. Kolagunta |
2008-08-12 |
|
| 7253484 |
Low-power multiple-channel fully depleted quantum well CMOSFETs |
James Pan, John G. Pellerin |
2007-08-07 |
$6,329,000 |
| 7238990 |
Interlayer dielectric under stress for an integrated circuit |
James D. Burnett |
2007-07-03 |
|
| 7235433 |
Silicon-on-insulator semiconductor device with silicon layers having different crystal orientations and method of forming the silicon-on-insulator semiconductor device |
Andrew Waite |
2007-06-26 |
$10,288,000 |
| 7208383 |
Method of manufacturing a semiconductor component |
Chad Weintraub, James F. Buller, Derick J. Wristers |
2007-04-24 |
$10,633,000 |
| 7179745 |
Method for offsetting a silicide process from a gate electrode of a semiconductor device |
Andrew Waite, David E. Brown |
2007-02-20 |
$8,070,000 |
| 7091106 |
Method of reducing STI divot formation during semiconductor device fabrication |
Douglas J. Bonser, Johannes Groschopf, Srikanteswara Dakshina-Murthy, John G. Pellerin |
2006-08-15 |
$18,169,000 |
| 7074657 |
Low-power multiple-channel fully depleted quantum well CMOSFETs |
James Pan, John G. Pellerin |
2006-07-11 |
$11,570,000 |
| 6833307 |
Method for manufacturing a semiconductor component having an early halo implant |
Derick J. Wristers, Chad Weintraub, James F. Buller |
2004-12-21 |
$5,396,000 |
| 6787464 |
Method of forming silicide layers over a plurality of semiconductor devices |
Scott Luning |
2004-09-07 |
$2,099,000 |
| 6720227 |
Method of forming source/drain regions in a semiconductor device |
Daniel Kadosh, James F. Buller, Basab Bandyopadhyay |
2004-04-13 |
$3,617,000 |
| 6674135 |
Semiconductor structure having elevated salicided source/drain regions and metal gate electrode on nitride/oxide dielectric |
Derick J. Wristers, Mark I. Gardner |
2004-01-06 |
$4,179,000 |
| 6638829 |
Semiconductor structure having a metal gate electrode and elevated salicided source/drain regions and a method for manufacture |
Derick J. Wristers, Mark I. Gardner |
2003-10-28 |
$6,461,000 |
| 6580122 |
Transistor device having an enhanced width dimension and a method of making same |
Derick J. Wristers, John G. Pellerin |
2003-06-17 |
$2,827,000 |
| 6566696 |
Self-aligned VT implant |
Mark W. Michael, Derick J. Wristers, James F. Buller |
2003-05-20 |
$2,116,000 |
| 6541321 |
Method of making transistors with gate insulation layers of differing thickness |
James F. Buller |
2003-04-01 |
$3,014,000 |
| 6506642 |
Removable spacer technique |
Scott Luning, Daniel Kadosh, James F. Buller, David E. Brown |
2003-01-14 |
$2,234,000 |
| 6426262 |
Method of analyzing the effects of shadowing of angled halo implants |
Mark B. Fuselier, Frederick N. Hause, Marilyn I. Wright |
2002-07-30 |
$3,277,000 |
| 6417539 |
High density memory cell assembly and methods |
Mark I. Gardner, Derick J. Wristers |
2002-07-09 |
$2,516,000 |
| 6406964 |
Method of controlling junction recesses in a semiconductor device |
Derick J. Wristers, John G. Pellerin |
2002-06-18 |
$3,499,000 |
| 6403979 |
Test structure for measuring effective channel length of a transistor |
Daniel Kadosh |
2002-06-11 |
$2,353,000 |
| 6399493 |
Method of silicide formation by silicon pretreatment |
Robert Dawson, John G. Pellerin |
2002-06-04 |
$2,015,000 |
