Issued Patents All Time
Showing 26–50 of 67 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6383872 | Parallel and series-coupled transistors having gate conductors formed on sidewall surfaces of a sacrificial structure | Daniel Kadosh, Mark I. Gardner | 2002-05-07 |
| 6372587 | Angled halo implant tailoring using implant mask | Scott Luning, Derick J. Wristers | 2002-04-16 |
| 6359461 | Test structure for determining the properties of densely packed transistors | John J. Bush, H. Jim Fulford | 2002-03-19 |
| 6358803 | Method of fabricating a deep source/drain | Mark W. Michael | 2002-03-19 |
| 6346426 | Method and apparatus for characterizing semiconductor device performance variations based on independent critical dimension measurements | Anthony J. Toprac, Derick J. Wristers | 2002-02-12 |
| 6323095 | Method for reducing junction capacitance using a halo implant photomask | Mark W. Michael, Robert Dawson | 2001-11-27 |
| 6316302 | Isotropically etching sidewall spacers to be used for both an NMOS source/drain implant and a PMOS LDD implant | Derick J. Wristers, Anthony J. Toprac | 2001-11-13 |
| 6300205 | Method of making a semiconductor device with self-aligned active, lightly-doped drain, and halo regions | H. Jim Fulford, Derick J. Wristers, James F. Buller | 2001-10-09 |
| 6274415 | Self-aligned Vt implant | Mark W. Michael, Derick J. Wristers, James F. Buller | 2001-08-14 |
| 6261936 | Poly gate CD passivation for metrology control | Marilyn I. Wright, Derick J. Wristers | 2001-07-17 |
| 6261885 | Method for forming integrated circuit gate conductors from dual layers of polysilicon | Daniel Kadosh, Mark W. Michael | 2001-07-17 |
| 6245649 | Method for forming a retrograde impurity profile | James F. Buller, Daniel Kadosh, Derick J. Wristers, H. Jim Fulford | 2001-06-12 |
| 6242330 | Process for breaking silicide stringers extending between silicide areas of different active regions | Derick J. Wristers, Fred N. Hause | 2001-06-05 |
| 6225201 | Ultra short transistor channel length dictated by the width of a sidewall spacer | Mark I. Gardner, Derrick J. Wristers, Thomas E. Spikes, Jr. | 2001-05-01 |
| 6191446 | Formation and control of a vertically oriented transistor channel length | Mark I. Gardner, John J. Bush | 2001-02-20 |
| 6180475 | Transistor formation with local interconnect overetch immunity | Derick J. Wristers, H. Jim Fulford | 2001-01-30 |
| 6162694 | Method of forming a metal gate electrode using replaced polysilicon structure | Derick J. Wristers, Mark I. Gardner | 2000-12-19 |
| 6159812 | Reduced boron diffusion by use of a pre-anneal | William A. Whigham, Derick J. Wristers | 2000-12-12 |
| 6137145 | Semiconductor topography including integrated circuit gate conductors incorporating dual layers of polysilicon | Daniel Kadosh, Mark W. Michael | 2000-10-24 |
| 6130454 | Gate conductor formed within a trench bounded by slanted sidewalls | Mark I. Gardner, John J. Bush | 2000-10-10 |
| 6124610 | Isotropically etching sidewall spacers to be used for both an NMOS source/drain implant and a PMOS LDD implant | Derick J. Wristers, Anthony J. Toprac | 2000-09-26 |
| 6118163 | Transistor with integrated poly/metal gate electrode | Mark I. Gardner, Derick J. Wristers | 2000-09-12 |
| 6114211 | Semiconductor device with vertical halo region and methods of manufacture | H. Jim Fulford, Derick J. Wristers, James F. Buller | 2000-09-05 |
| 6110786 | Semiconductor device having elevated gate electrode and elevated active regions and method of manufacture thereof | Mark I. Gardner, John J. Bush | 2000-08-29 |
| 6104077 | Semiconductor device having gate electrode with a sidewall air gap | Mark I. Gardner, Derick J. Wristers | 2000-08-15 |