Issued Patents All Time
Showing 51–67 of 67 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6104064 | Asymmetrical transistor structure | Daniel Kadosh, Mark I. Gardner, Michael Duane, Fred N. Hause, Robert Dawson +1 more | 2000-08-15 |
| 6074906 | Complementary metal-oxide semiconductor device having source/drain regions formed using multiple spacers | Derick J. Wristers, H. Jim Fulford | 2000-06-13 |
| 6075417 | Ring oscillator test structure | Antonio Torres Garcia, John J. Bush | 2000-06-13 |
| 6037629 | Trench transistor and isolation trench | Mark I. Gardner, Daniel Kadosh | 2000-03-14 |
| 6018180 | Transistor formation with LI overetch immunity | Derick J. Wristers, H. Jim Fulford | 2000-01-25 |
| 5994193 | Method of making high performance MOSFET with integrated poly/metal gate electrode | Mark I. Gardner, Derick J. Wristers | 1999-11-30 |
| 5986283 | Test structure for determining how lithographic patterning of a gate conductor affects transistor properties | John J. Bush, Mark I. Gardner | 1999-11-16 |
| 5981365 | Stacked poly-oxide-poly gate for improved silicide formation | Derick J. Wristers, Mark I. Gardner | 1999-11-09 |
| 5977600 | Formation of shortage protection region | Derick J. Wristers, H. James Fulford | 1999-11-02 |
| 5935766 | Method of forming a conductive plug in an interlevel dielectric | Daniel Kadosh, Derick J. Wristers | 1999-08-10 |
| 5930592 | Asymmetrical n-channel transistor having LDD implant only in the drain region | Daniel Kadosh, Brad Moore | 1999-07-27 |
| 5926693 | Two level transistor formation for optimum silicon utilization | Mark I. Gardner, Fred N. Hause | 1999-07-20 |
| 5893739 | Asymmetrical P-channel transistor having a boron migration barrier and a selectively formed sidewall spacer | Daniel Kadosh, Fred N. Hause | 1999-04-13 |
| 5866934 | Parallel and series-coupled transistors having gate conductors formed on sidewall surfaces of a sacrificial structure | Daniel Kadosh, Mark I. Gardner | 1999-02-02 |
| 5852310 | Multi-level transistor fabrication method with a patterned upper transistor substrate and interconnection thereto | Daniel Kadosh, Mark I. Garnder | 1998-12-22 |
| 5780340 | Method of forming trench transistor and isolation trench | Mark I. Gardner, Daniel Kadosh | 1998-07-14 |
| 5770482 | Multi-level transistor fabrication method with a patterned upper transistor substrate and interconnection thereto | Daniel Kadosh, Mark I. Garnder | 1998-06-23 |