| 8687417 |
Electronic device and method of biasing |
Ruigang Li, Jingrong Zhou, David Wu, Zhonghai Shi, James F. Buller +2 more |
2014-04-01 |
$6,826,000 |
| 8564120 |
Heat dissipation in temperature critical device areas of semiconductor devices by heat pipes connecting to the substrate backside |
Anthony Mowry, David Gerald Farber, Markus Lenski |
2013-10-22 |
$1,818,000 |
| 7804107 |
Thyristor semiconductor device and method of manufacture |
Andrew E. Horch |
2010-09-28 |
|
| 7745337 |
Method of optimizing sidewall spacer size for silicide proximity with in-situ clean |
David Gerald Farber, Markus Lenski, Anthony Mowry |
2010-06-29 |
$10,708,000 |
| 7741663 |
Air gap spacer formation |
Anthony Mowry, David Gerald Farber, Markus Lenski |
2010-06-22 |
$10,015,000 |
| 7670932 |
MOS structures with contact projections for lower contact resistance and methods for fabricating the same |
Jianhong Zhu, David Wu |
2010-03-02 |
$5,781,000 |
| 7279367 |
Method of manufacturing a thyristor semiconductor device |
Andrew E. Horch |
2007-10-09 |
|
| 6967160 |
Method of manufacturing semiconductor device having nickel silicide with reduced interface roughness |
Eric N. Paton, Paul R. Besser, Simon S. Chan |
2005-11-22 |
$6,256,000 |
| 6888176 |
Thyrister semiconductor device |
Andrew E. Horch |
2005-05-03 |
|
| 6873051 |
Nickel silicide with reduced interface roughness |
Eric N. Paton, Paul R. Besser, Simon S. Chan |
2005-03-29 |
$4,814,000 |
| 6661061 |
Integrated circuit with differing gate oxide thickness |
Mark I. Gardner |
2003-12-09 |
$2,702,000 |
| 6559028 |
Method of topography management in semiconductor formation |
Michael Allen |
2003-05-06 |
$2,132,000 |
| 6376330 |
Dielectric having an air gap formed between closely spaced interconnect lines |
H. Jim Fulford, Robert Dawson, Basab Bandyopadhyay, Mark W. Michael, William S. Brennan |
2002-04-23 |
$2,653,000 |
| 6365943 |
High density integrated circuit |
Mark I. Gardner, Daniel Kadosh |
2002-04-02 |
$3,760,000 |
| 6353253 |
Semiconductor isolation region bounded by a trench and covered with an oxide to improve planarization |
Basab Bandyopadhyay, H. Jim Fulford, Robert Dawson, Mark W. Michael, William S. Brennan |
2002-03-05 |
$11,927,000 |
| 6326298 |
Substantially planar semiconductor topography using dielectrics and chemical mechanical polish |
Robert Dawson, Mark W. Michael, Basab Bandyopadhyay, H. Jim Fulford, William S. Brennan |
2001-12-04 |
$4,361,000 |
| 6323561 |
Spacer formation for precise salicide formation |
Mark I. Gardner, Charles E. May |
2001-11-27 |
$5,286,000 |
| 6288432 |
Semiconductor fabrication employing a post-implant anneal within a low temperature, high pressure nitrogen ambient to improve channel and gate oxide reliability |
Mark I. Gardner |
2001-09-11 |
|
| 6255215 |
Semiconductor device having silicide layers formed using a collimated metal layer |
Charles E. May, William S. Brennan |
2001-07-03 |
$7,468,000 |
| 6242330 |
Process for breaking silicide stringers extending between silicide areas of different active regions |
Jon D. Cheek, Derick J. Wristers |
2001-06-05 |
$7,807,000 |
| 6225168 |
Semiconductor device having metal gate electrode and titanium or tantalum nitride gate dielectric barrier layer and process of fabrication thereof |
Mark I. Gardner, H. Jim Fulford, Charles E. May, Dim-Lee Kwong |
2001-05-01 |
$7,851,000 |
| 6208015 |
Interlevel dielectric with air gaps to lessen capacitive coupling |
Basab Bandyopadhyay, H. Jim Fulford, Robert Dawson, Mark W. Michael, William S. Brennan |
2001-03-27 |
$5,495,000 |
| 6184566 |
Method and structure for isolating semiconductor devices after transistor formation |
Mark I. Gardner, H. Jim Fulford |
2001-02-06 |
$6,888,000 |
| 6171917 |
Transistor sidewall spacers composed of silicon nitride CVD deposited from a high density plasma source |
Sey-Ping Sun, Thomas E. Spikes, Jr. |
2001-01-09 |
$4,016,000 |
| 6165858 |
Enhanced silicidation formation for high speed MOS device by junction grading with dual implant dopant species |
Mark I. Gardner, Jon Cheek |
2000-12-26 |
$2,711,000 |
