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USPTO Patent Rankings Data through Dec 31, 2025
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Charles E. May — 117 Patents

AMD: 92 patents #37 of 9,280Top 1%
LSLsi: 20 patents #124 of 3,238Top 4%
UKUniversity Of Kentucky: 1 patents #424 of 1,057Top 45%
NASA: 1 patents #1,837 of 3,881Top 50%
Rocky River, OH: #2 of 263 inventorsTop 1%
Ohio: #130 of 73,341 inventorsTop 1%
Overall (All Time): #10,533 of 4,157,543Top 1%
117 Patents All Time
Charles E. May has been granted 117 US patents while listed as an inventor at AMD. The first was granted in 1980 and the most recent in July 2015. Charles E. May ranks #10,533 of 4,157,543 US inventors in our database (top 0.25%). Patent records list Charles E. May in Rocky River, OH, US.

Issued Patents All Time

Showing 1–25 of 117 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
9087945 Nanowires, nanowire junctions, and methods of making the same Vijay Pal Singh, Suresh K S Rajaputra 2015-07-21
7601643 Arrangement and method for fabricating a semiconductor wafer 2009-10-13 $11,591,000
7582566 Method for redirecting void diffusion away from vias in an integrated circuit design Derryl D. J. Allman, Hemanshu Bhatt, Peter A. Burke, Byung Sung Kwak, Sey-Shing Sun +2 more 2009-09-01 $5,881,000
7436040 Method and apparatus for diverting void diffusion in integrated circuit conductors Derryl D. J. Allman, Hemanshu Bhatt, Peter A. Burke, Byung Sung Kwak, Sey-Shing Sun +2 more 2008-10-14 $11,302,000
7361965 Method and apparatus for redirecting void diffusion away from vias in an integrated circuit design Derryl D. J. Allman, Hemanshu Bhatt, Peter A. Burke, Byung Sung Kwak, Sey-Shing Sun +2 more 2008-04-22 $4,481,000
7358594 Method of forming a low k polymer E-beam printable mechanical support Derryl J. Allman 2008-04-15 $10,580,000
7023067 Bond pad design Derryl D. J. Allman 2006-04-04 $3,131,000
6972217 Low k polymer E-beam printable mechanical support Derryl J. Allman 2005-12-06 $2,844,000
6967177 Temperature control system Hemanshu Bhatt 2005-11-22 $4,910,000
6875693 Via and metal line interface capable of reducing the incidence of electro-migration induced voids Wilbur G. Catabay 2005-04-05 $3,773,000
6743688 High performance MOSFET with modulated channel gate thickness Mark I. Gardner, H. James Fulford 2004-06-01 $2,717,000
6707114 Semiconductor wafer arrangement of a semiconductor wafer Hemanshu Bhatt 2004-03-16 $6,885,000
6654226 Thermal low k dielectrics Derryl D. J. Allman 2003-11-25 $4,689,000
6638776 Thermal characterization compensation 2003-10-28 $9,204,000
6620729 Ion beam dual damascene process 2003-09-16 $7,469,000
6566244 Process for improving mechanical strength of layers of low k dielectric material Venkatesh P. Gopinath, Peter J. Wright 2003-05-20 $2,301,000
6560504 Use of contamination-free manufacturing data in fault detection and classification as well as in run-to-run control Thomas J. Goodwin, Iraj Emami 2003-05-06 $2,132,000
6544829 Polysilicon gate salicidation Venkatesh P. Gopinath, Mohammad Mirabedini, Arvind Kamath 2003-04-08 $3,257,000
6531364 Advanced fabrication technique to form ultra thin gate dielectric using a sacrificial polysilicon seed layer Mark I. Gardner, H. Jim Fulford 2003-03-11 $2,325,000
6521520 Semiconductor wafer arrangement and method of processing a semiconductor wafer Hemanshu Bhatt 2003-02-18 $6,683,000
6495881 Programmable read only memory in CMOS process flow Shafqat Ahmed, Hemanshu Bhatt, Robindranath Banerjee 2002-12-17 $2,785,000
6482075 Process for planarizing an isolation structure in a substrate Hemanshu Bhatt, Shafqat Ahmed, Robindranath Banerjee 2002-11-19 $4,197,000
6451657 Transistor with an ultra short channel length defined by a laterally diffused nitrogen implant Mark I. Gardner, H. Jim Fulford 2002-09-17 $1,456,000
6452412 Drop-in test structure and methodology for characterizing an integrated circuit process flow and topography Richard W. Jarvis, Iraj Emami 2002-09-17 $1,456,000
6432812 Method of coupling capacitance reduction 2002-08-13 $4,311,000