Issued Patents All Time
Showing 25 most recent of 117 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9087945 | Nanowires, nanowire junctions, and methods of making the same | Vijay Pal Singh, Suresh K S Rajaputra | 2015-07-21 |
| 7601643 | Arrangement and method for fabricating a semiconductor wafer | — | 2009-10-13 |
| 7582566 | Method for redirecting void diffusion away from vias in an integrated circuit design | Derryl D. J. Allman, Hemanshu Bhatt, Peter A. Burke, Byung Sung Kwak, Sey-Shing Sun +2 more | 2009-09-01 |
| 7436040 | Method and apparatus for diverting void diffusion in integrated circuit conductors | Derryl D. J. Allman, Hemanshu Bhatt, Peter A. Burke, Byung Sung Kwak, Sey-Shing Sun +2 more | 2008-10-14 |
| 7361965 | Method and apparatus for redirecting void diffusion away from vias in an integrated circuit design | Derryl D. J. Allman, Hemanshu Bhatt, Peter A. Burke, Byung Sung Kwak, Sey-Shing Sun +2 more | 2008-04-22 |
| 7358594 | Method of forming a low k polymer E-beam printable mechanical support | Derryl J. Allman | 2008-04-15 |
| 7023067 | Bond pad design | Derryl D. J. Allman | 2006-04-04 |
| 6972217 | Low k polymer E-beam printable mechanical support | Derryl J. Allman | 2005-12-06 |
| 6967177 | Temperature control system | Hemanshu Bhatt | 2005-11-22 |
| 6875693 | Via and metal line interface capable of reducing the incidence of electro-migration induced voids | Wilbur G. Catabay | 2005-04-05 |
| 6743688 | High performance MOSFET with modulated channel gate thickness | Mark I. Gardner, H. James Fulford | 2004-06-01 |
| 6707114 | Semiconductor wafer arrangement of a semiconductor wafer | Hemanshu Bhatt | 2004-03-16 |
| 6654226 | Thermal low k dielectrics | Derryl D. J. Allman | 2003-11-25 |
| 6638776 | Thermal characterization compensation | — | 2003-10-28 |
| 6620729 | Ion beam dual damascene process | — | 2003-09-16 |
| 6566244 | Process for improving mechanical strength of layers of low k dielectric material | Venkatesh P. Gopinath, Peter J. Wright | 2003-05-20 |
| 6560504 | Use of contamination-free manufacturing data in fault detection and classification as well as in run-to-run control | Thomas J. Goodwin, Iraj Emami | 2003-05-06 |
| 6544829 | Polysilicon gate salicidation | Venkatesh P. Gopinath, Mohammad Mirabedini, Arvind Kamath | 2003-04-08 |
| 6531364 | Advanced fabrication technique to form ultra thin gate dielectric using a sacrificial polysilicon seed layer | Mark I. Gardner, H. Jim Fulford | 2003-03-11 |
| 6521520 | Semiconductor wafer arrangement and method of processing a semiconductor wafer | Hemanshu Bhatt | 2003-02-18 |
| 6495881 | Programmable read only memory in CMOS process flow | Shafqat Ahmed, Hemanshu Bhatt, Robindranath Banerjee | 2002-12-17 |
| 6482075 | Process for planarizing an isolation structure in a substrate | Hemanshu Bhatt, Shafqat Ahmed, Robindranath Banerjee | 2002-11-19 |
| 6451657 | Transistor with an ultra short channel length defined by a laterally diffused nitrogen implant | Mark I. Gardner, H. Jim Fulford | 2002-09-17 |
| 6452412 | Drop-in test structure and methodology for characterizing an integrated circuit process flow and topography | Richard W. Jarvis, Iraj Emami | 2002-09-17 |
| 6432812 | Method of coupling capacitance reduction | — | 2002-08-13 |