Issued Patents All Time
Showing 1–25 of 27 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12148474 | Apparatus and methods including source gates | Akira Goda, Khaled Hasnat, Krishna K. Parat | 2024-11-19 |
| 11500446 | Reducing power consumption in nonvolatile memory due to standby leakage current | Richard Fastow, Shankar Natarajan, Chang Wan Ha, Chee Kwa LAW, Khaled Hasnat +1 more | 2022-11-15 |
| 11322546 | Current delivery and spike mitigation in a memory cell array | Kiran Pangal | 2022-05-03 |
| 11211126 | Apparatus and methods including source gates | Akira Goda, Khaled Hasnat, Krishna K. Parat | 2021-12-28 |
| 11029861 | Sense flags in a memory device | Khaled Hasnat, Pranav Kalavade, Krishna K. Parat, Aaron Yip, Mark A. Helm +1 more | 2021-06-08 |
| 10783967 | Apparatus and methods including source gates | Akira Goda, Khaled Hasnat, Krishna K. Parat | 2020-09-22 |
| 10409506 | Sense flags in a memory device | Khaled Hasnat, Pranav Kalavade, Krishna K. Parat, Aaron Yip, Mark A. Helm +1 more | 2019-09-10 |
| 10170189 | Apparatus and methods including source gates | Akira Goda, Khaled Hasnat, Krishna K. Parat | 2019-01-01 |
| 10126967 | Sense operation flags in a memory device | Khaled Hasnat, Pranav Kalavade, Krishna K. Parat, Aaron Yip, Mark A. Helm +1 more | 2018-11-13 |
| 9779816 | Apparatus and methods including source gates | Akira Goda, Khaled Hasnat, Krishna K. Parat | 2017-10-03 |
| 9519582 | Sense operation flags in a memory device | Khaled Hasnat, Pranav Kalavade, Krishna K. Parat, Aaron Yip, Mark A. Helm +1 more | 2016-12-13 |
| 9378839 | Apparatus and methods including source gates | Akira Goda, Khaled Hasnat, Krishna K. Parat | 2016-06-28 |
| 9135998 | Sense operation flags in a memory device | Khaled Hasnat, Pranav Kalavade, Krishna K. Parat, Aaron Yip, Mark A. Helm +1 more | 2015-09-15 |
| 8797806 | Apparatus and methods including source gates | Akira Goda, Khaled Hasnat, Krishna K. Parat | 2014-08-05 |
| 8498159 | Independent well bias management in a memory device | Akira Goda, Tomoharu Tanaka, Krishna K. Parat, Prashant S. Damle | 2013-07-30 |
| 8174893 | Independent well bias management in a memory device | Akira Goda, Tomoharu Tanaka, Krishna K. Parat, Prashant S. Damle | 2012-05-08 |
| 7972909 | Guard ring extension to prevent reliability failures | Nicole Meier Chang, George J. Korsh, John Nugent, Ed Nabighian | 2011-07-05 |
| 7968976 | Guard ring extension to prevent reliability failures | Nicole Meier Chang, George J. Korsh, John Nugent, Ed Nabighian | 2011-06-28 |
| 7920419 | Isolated P-well architecture for a memory device | Prashant S. Damle, Krishna K. Parat | 2011-04-05 |
| 7566915 | Guard ring extension to prevent reliability failures | Nicole Meier Chang, George J. Korsh, John Nugent, Ed Nabighian | 2009-07-28 |
| 6911695 | Transistor having insulating spacers on gate sidewalls to reduce overlap between the gate and doped extension regions of the source and drain | Henry Chao, Derchang Kau | 2005-06-28 |
| 6537923 | Process for forming integrated circuit structure with low dielectric constant material between closely spaced apart metal lines | Hemanshu Bhatt, Robindranath Banerjee | 2003-03-25 |
| 6495419 | Nonvolatile memory in CMOS process flow | Hemanshu Bhatt, Robindranath Banerjee | 2002-12-17 |
| 6495881 | Programmable read only memory in CMOS process flow | Hemanshu Bhatt, Charles E. May, Robindranath Banerjee | 2002-12-17 |
| 6482075 | Process for planarizing an isolation structure in a substrate | Hemanshu Bhatt, Robindranath Banerjee, Charles E. May | 2002-11-19 |