Issued Patents All Time
Showing 25 most recent of 92 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12340847 | Flash memory chip that modulates its program step voltage as a function of chip temperature | Arash Hazeghi, Rohit S. Shenoy, Hsiao-Yu Chang | 2025-06-24 |
| 12334152 | Simultaneous programming of multiple sub-blocks in NAND memory structures | Ali Khakifirooz, Shantanu R. Rajwade, Tarek Ahmed Ameen Beshari | 2025-06-17 |
| 12243590 | Method and apparatus for improving write uniformity in a memory device | Shantanu R. Rajwade, Christian Mion, Rohit S. Shenoy, Xin Sun, Kristopher H. Gaewsky | 2025-03-04 |
| 12224019 | Cache processes with adaptive dynamic start voltage calculation for memory devices | Xiang Yang, Ali Khakifirooz, Shantanu R. Rajwade | 2025-02-11 |
| 12106815 | Variable error correction codeword packing to support bit error rate targets | Ravi H. Motwani, Rohit S. Shenoy, Rifat Ferdous | 2024-10-01 |
| 11923010 | Flash memory chip that modulates its program step voltage as a function of chip temperature | Arash Hazeghi, Rohit S. Shenoy, Hsiao-Yu Chang | 2024-03-05 |
| 11721396 | Configuration of a memory device for programming memory cells | Violante Moschiano, Purval S. Sule, Han Liu, Andrea D'Alessandro, Han Zhao +1 more | 2023-08-08 |
| 11698725 | Apparatuses and methods for concurrently accessing multiple memory planes of a memory during a memory access operation | Shantanu R. Rajwade, Toru Tanzawa | 2023-07-11 |
| 11625191 | Apparatuses, systems, and methods for heating a memory device | Arash Hazeghi, Rohit S. Shenoy, Krishna K. Parat | 2023-04-11 |
| 11587874 | Resistance reduction for word lines in memory arrays | Sung-Taeg Kang, Owen W. Jungroth, Prasanna Srinivasan | 2023-02-21 |
| 11429469 | Defective bit line management in connection with a memory access | Ali Khakifirooz, Ravi H. Motwani, Chang Wan Ha | 2022-08-30 |
| 11315644 | String current reduction during multistrobe sensing to reduce read disturb | Rohit S. Shenoy, Golnaz Karbasian | 2022-04-26 |
| 11270778 | Method and system for reducing program disturb degradation in flash memory | Han Zhao, Krishna K. Parat | 2022-03-08 |
| 11182074 | Apparatuses and methods for concurrently accessing multiple memory planes of a memory during a memory access operation | Shantanu R. Rajwade, Toru Tanzawa | 2021-11-23 |
| 11056203 | Boosted bitlines for storage cell programmed state verification in a memory array | Xiang Yang, Ali Khakifirooz, Shantanu R. Rajwade, Sagar Upadhyay | 2021-07-06 |
| 11029861 | Sense flags in a memory device | Shafqat Ahmed, Khaled Hasnat, Krishna K. Parat, Aaron Yip, Mark A. Helm +1 more | 2021-06-08 |
| 10942799 | Defective bit line management in connection with a memory access | Ali Khakifirooz, Ravi H. Motwani, Chang Wan Ha | 2021-03-09 |
| 10871903 | Achieving consistent read times in multi-level non-volatile memory | Anand S. Ramalingam | 2020-12-22 |
| 10839916 | One-sided soft reads | Zion S. Kwok, Ravi H. Motwani | 2020-11-17 |
| 10832766 | Program verification time reduction in non-volatile memory devices | Ali Khakifirooz, Uday Chandrasekhar, Trupti Bemalkhedkar, Chang Wan Ha | 2020-11-10 |
| 10777277 | Configuration of a memory device for programming memory cells | Violante Moschiano, Purval S. Sule, Han Liu, Andrea D'Alessandro, Han Zhao +1 more | 2020-09-15 |
| 10699790 | Erase and soft program for vertical NAND flash | Krishna K. Parat, Koichi Kawai, Akira Goda | 2020-06-30 |
| 10658053 | Ramping inhibit voltage during memory programming | Shantanu R. Rajwade, Neal R. Mielke, Krishna K. Parat, Shyam Sunder Raghunathan | 2020-05-19 |
| 10629271 | Method and system for reducing program disturb degradation in flash memory | Han Zhao, Krishna K. Parat | 2020-04-21 |
| 10599515 | Transfer of encoded data stored in non-volatile memory for decoding by a controller of a memory device | Ravi H. Motwani | 2020-03-24 |