PK

Pranav Kalavade

IN Intel: 59 patents #501 of 30,777Top 2%
Micron: 28 patents #656 of 6,345Top 15%
AS Agere Systems: 2 patents #639 of 1,849Top 35%
SS Sk Hynix Nand Product Solutions: 2 patents #26 of 148Top 20%
📍 San Jose, CA: #306 of 32,062 inventorsTop 1%
🗺 California: #2,615 of 386,348 inventorsTop 1%
Overall (All Time): #17,025 of 4,157,543Top 1%
92
Patents All Time

Issued Patents All Time

Showing 51–75 of 92 patents

Patent #TitleCo-InventorsDate
9865357 Performing read operations on a memory device Deepak Thimmegowda, Aaron Yip, Shantanu R. Rajwade 2018-01-09
9851905 Concurrent memory operations for read operation preemption Anand S. Ramalingam, Aliasgar S. Madraswala 2017-12-26
9852065 Method and apparatus for reducing data program completion overhead in NAND flash Shantanu R. Rajwade, Andrea D'Alessandro, Violante Moschiano 2017-12-26
9819362 Apparatus and method for detecting and mitigating bit-line opens in flash memory Ravi H. Motwani 2017-11-14
9811269 Achieving consistent read times in multi-level non-volatile memory Anand S. Ramalingam 2017-11-07
9792997 Ramping inhibit voltage during memory programming Shantanu R. Rajwade, Neal R. Mielke, Krishna K. Parat, Shyam Sunder Raghunathan 2017-10-17
9754683 Method and system to obtain state confidence data using multistrobe read of a non-volatile memory Matthew Goldman, Krishna K. Parat, Nathan Franklin, Mark A. Helm 2017-09-05
9740419 Methods and apparatus to preserve data of a solid state drive during a power loss event Yogesh B. Wakchaure, Aliasgar S. Madraswala, Xin Guo, David J. Pelster, Myron Loewen +2 more 2017-08-22
9703494 Method and apparatus for protecting lower page data during programming in NAND flash Shantanu R. Rajwade 2017-07-11
9672102 NAND memory devices systems, and methods using pre-read error recovery protocols of upper and lower pages Akira Goda, Charan Srinivasan 2017-06-06
9576674 Memory cell sensing Matthew Goldman, Uday Chandrasekhar, Mark A. Helm 2017-02-21
9570159 Methods and apparatus to preserve data of a solid state drive during a power loss event Yogesh B. Wakchaure, Aliasgar S. Madraswala, Xin Guo, David J. Pelster, Myron Loewen +2 more 2017-02-14
9535777 Defect management policies for NAND flash memory Feng Zhu, Shyam Sunder Raghunathan, Ravi H. Motwani 2017-01-03
9519582 Sense operation flags in a memory device Shafqat Ahmed, Khaled Hasnat, Krishna K. Parat, Aaron Yip, Mark A. Helm +1 more 2016-12-13
9484101 Methods of programming memories Akira Goda, Tommaso Vali, Violante Moschiano 2016-11-01
9418000 Dynamically compensating for degradation of a non-volatile memory device Shyam Sunder Raghunathan, Iwen Chao, Xin Guo, Krishna K. Parat, Feng Zhu 2016-08-16
9418752 Ramping inhibit voltage during memory programming Shantanu R. Rajwade, Neal R. Mielke, Krishna K. Parat, Shyam Sunder Raghunathan 2016-08-16
9396791 Programming memories with multi-level pass signal Shyam Sunder Raghunathan, Krishna K. Parat, Charan Srinivasan 2016-07-19
9330777 Memory program disturb reduction Akira Goda, Mark A. Helm, Charan Srinivasan 2016-05-03
9305654 Erase and soft program for vertical NAND flash Krishna K. Parat, Koichi Kawai, Akira Goda 2016-04-05
9245645 Multi-pulse programming for memory Charan Srinivasan, Shyam Sunder Raghunathan, Krishna K. Parat 2016-01-26
9230666 Drain select gate voltage management Akira Goda, Doyle Rivers 2016-01-05
9135998 Sense operation flags in a memory device Shafqat Ahmed, Khaled Hasnat, Krishna K. Parat, Aaron Yip, Mark A. Helm +1 more 2015-09-15
9105337 Memories and methods of programming memories Akira Goda, Tommaso Vali, Violante Moschiano 2015-08-11
9099183 Program VT spread folding for NAND flash memory programming Charan Srinivasan, Shyam Sunder Raghunathan, Krishna K. Parat 2015-08-04