Issued Patents All Time
Showing 25 most recent of 149 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12271592 | Independent plane architecture in a memory device | Andrea Giovanni Xotta, Dheeraj Srinivasan, Ali Mohammadzadeh, Karl D. Schuh, Guido Luciano Rizzo +7 more | 2025-04-08 |
| 12131782 | 3D memory device including shared select gate connections between memory blocks | — | 2024-10-29 |
| 12125786 | Devices including stair step structures, and related memory devices and electronic systems | Paolo Tessariol, Graham R. Wolstenholme | 2024-10-22 |
| 12114499 | Block-on-block memory array architecture using bi-directional staircases | — | 2024-10-08 |
| 12080351 | Using non-segregated cells as drain-side select gates for sub-blocks in a memory device | — | 2024-09-03 |
| 12080360 | Reducing programming disturbance in memory devices | — | 2024-09-03 |
| 12080700 | Microelectronic devices including control logic regions | Kunal R. Parekh, Akira Goda | 2024-09-03 |
| 12068272 | Microelectronic devices having a memory array region, a control logic region, and signal routing structures | Akira Goda, Kunal R. Parekh | 2024-08-20 |
| 11915758 | Memory devices with four data line bias levels | Hao Thai Nguyen, Tomoko Ogura Iwasaki, Erwin E. Yu, Dheeraj Srinivasan, Sheyang Ning +2 more | 2024-02-27 |
| 11688470 | Reducing programming disturbance in memory devices | — | 2023-06-27 |
| 11688463 | Vertical string driver for memory array | Tomoko Ogura Iwasaki | 2023-06-27 |
| 11670370 | 3D memory device including shared select gate connections between memory blocks | — | 2023-06-06 |
| 11636886 | Memory devices with user-defined tagging mechanism | Theodore T. Pekny | 2023-04-25 |
| 11605588 | Memory device including data lines on multiple device levels | Violante Moschiano, Paolo Tessariol, Naveen Kaushik | 2023-03-14 |
| 11587919 | Microelectronic devices, related electronic systems, and methods of forming microelectronic devices | Kunal R. Parekh, Akira Goda | 2023-02-21 |
| 11574685 | Apparatus for memory cell programming | — | 2023-02-07 |
| 11562791 | Memory devices with four data line bias levels | Hao Thai Nguyen, Tomoko Ogura Iwasaki, Erwin E. Yu, Dheeraj Srinivasan, Sheyang Ning +2 more | 2023-01-24 |
| 11557080 | Dynamically modeling an object in an environment from different perspectives | Xiaoyi Huang | 2023-01-17 |
| 11545456 | Microelectronic devices, electronic systems having a memory array region and a control logic region, and methods of forming microelectronic devices | Akira Goda, Kunal R. Parekh | 2023-01-03 |
| 11430734 | Methods of forming memory devices including stair step structures | Paolo Tessariol, Graham R. Wolstenholme | 2022-08-30 |
| 11404125 | Memory cell programming applying a programming pulse having different voltage levels | — | 2022-08-02 |
| 11342034 | Reducing programming disturbance in memory devices | — | 2022-05-24 |
| 11335700 | Block-on-block memory array architecture using bi-directional staircases | — | 2022-05-17 |
| 11329058 | Microelectronic devices and memory devices | — | 2022-05-10 |
| 11302397 | Memory block select circuitry including voltage bootstrapping control | — | 2022-04-12 |