Issued Patents All Time
Showing 51–75 of 149 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10467817 | User device augmented reality virtual item modeling | — | 2019-11-05 |
| 10418072 | Memories having select devices between access lines and in memory cells | — | 2019-09-17 |
| 10409506 | Sense flags in a memory device | Shafqat Ahmed, Khaled Hasnat, Pranav Kalavade, Krishna K. Parat, Mark A. Helm +1 more | 2019-09-10 |
| 10347049 | Interactive item placement simulation | Guy Shaviv, Xiaoyi Huang | 2019-07-09 |
| 10332601 | Erasing memory cells sequentially | — | 2019-06-25 |
| 10332603 | Access line management in a memory device | Benjamin Louie, Ali Mohammadzadeh | 2019-06-25 |
| 10289484 | Apparatuses and methods for generating probabilistic information with current integration sensing | Patrick R. Khayat, Sivagnanam Parthasarathy, Mustafa N. Kaynak, Mark A. Helm | 2019-05-14 |
| 10290581 | Methods of forming conductive structures including stair step or tiered structures having conductive portions | Paolo Tessariol, Graham R. Wolstenholme | 2019-05-14 |
| 10262745 | Apparatuses and methods using dummy cells programmed to different states | Toru Tanzawa | 2019-04-16 |
| 10249345 | Memories having select devices between access lines and in memory cells | — | 2019-04-02 |
| 10186325 | Method and apparatus for shielded read to reduce parasitic capacitive coupling | Mark A. Helm | 2019-01-22 |
| 10170188 | 3D memory device including shared select gate connections between memory blocks | — | 2019-01-01 |
| 10126967 | Sense operation flags in a memory device | Shafqat Ahmed, Khaled Hasnat, Pranav Kalavade, Krishna K. Parat, Mark A. Helm +1 more | 2018-11-13 |
| 10102657 | Generating enhanced images using dimensional data | Xiaoyi Huang | 2018-10-16 |
| 10079064 | Apparatuses and methods using dummy cells programmed to different states | Toru Tanzawa | 2018-09-18 |
| 10049705 | Memories having select devices between access lines and in memory cells formed of a same type of circuit element | — | 2018-08-14 |
| 10043751 | Three dimensional storage cell array with highly dense and scalable word line design approach | Deepak Thimmegowda, Mark A. Helm, Yongna Li | 2018-08-07 |
| 10037806 | Memory cell programming using VgVt value | — | 2018-07-31 |
| 10014061 | Methods and apparatus having multiple select gates of different ranges of threshold voltages connected in series with memory cells | Mark A. Helm | 2018-07-03 |
| 9941209 | Conductive structures, systems and devices including conductive structures and related methods | Paolo Tessariol, Graham R. Wolstenholme | 2018-04-10 |
| 9875802 | Access line management in a memory device | Benjamin Louie, Ali Mohammadzadeh | 2018-01-23 |
| 9865357 | Performing read operations on a memory device | Deepak Thimmegowda, Pranav Kalavade, Shantanu R. Rajwade | 2018-01-09 |
| 9767909 | Memory cell programming utilizing conditional enabling of memory cells | — | 2017-09-19 |
| 9721622 | Systems with memory segmentation and systems with biasing lines to receive same voltages during accessing | — | 2017-08-01 |
| 9697907 | Apparatuses and methods using dummy cells programmed to different states | Toru Tanzawa | 2017-07-04 |