Issued Patents All Time
Showing 25 most recent of 130 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12171093 | NAND string utilizing floating body memory cell | Jin-Woo Han, Yuniarto Widjaja | 2024-12-17 |
| 12080349 | Content addressable memory device having electrically floating body transistor | Jin-Woo Han, Yuniarto Widjaja | 2024-09-03 |
| 12062392 | Scalable floating body memory cell for memory compilers and method of using floating body memories with memory compilers | Yuniarto Widjaja, Zvi Or-Bach | 2024-08-13 |
| 11985809 | Memory device having electrically floating body transistor | Yuniarto Widjaja, Jin-Woo Han | 2024-05-14 |
| 11974425 | Memory cell comprising first and second transistors and methods of operating | Yuniarto Widjaja, Jin-Woo Han | 2024-04-30 |
| 11941299 | MRAM access coordination systems and methods via pipeline in parallel | Neal Berger, Lester Crudele | 2024-03-26 |
| 11881264 | Content addressable memory device having electrically floating body transistor | Jin-Woo Han, Yuniarto Widjaja | 2024-01-23 |
| 11818878 | NAND string utilizing floating body memory cell | Jin-Woo Han, Yuniarto Widjaja | 2023-11-14 |
| 11769550 | Systems and methods for reducing standby power in floating body memory devices | Yuniarto Widjaja | 2023-09-26 |
| 11699484 | Scalable floating body memory cell for memory compilers and method of using floating body memories with memory compilers | Yuniarto Widjaja, Zvi Or-Bach | 2023-07-11 |
| 11594280 | Content addressable memory device having electrically floating body transistor | Jin-Woo Han, Yuniarto Widjaja | 2023-02-28 |
| 11423965 | Word line decoder memory architecture | Neal Berger, Susmita Karmakar | 2022-08-23 |
| 11417658 | NAND string utilizing floating body memory cell | Jin-Woo Han, Yuniarto Widjaja | 2022-08-16 |
| 11417657 | Memory device having electrically floating body transistor | Yuniarto Widjaja, Jin-Woo Han | 2022-08-16 |
| 11386010 | Circuit engine for managing memory meta-stability | Neal Berger, Lester Crudele | 2022-07-12 |
| 11348922 | Memory cell comprising first and second transistors and methods of operating | Yuniarto Widjaja, Jin-Woo Han | 2022-05-31 |
| 11342018 | Systems and methods for reducing standby power in floating body memory devices | Yuniarto Widjaja | 2022-05-24 |
| 11334288 | MRAM access coordination systems and methods with a plurality of pipelines | Neal Berger, Lester Crudele | 2022-05-17 |
| 11217300 | Scalable floating body memory cell for memory compilers and method of using floating body memories with memory compilers | Yuniarto Widjaja, Zvi Or-Bach | 2022-01-04 |
| 11151042 | Error cache segmentation for power reduction | Neal Berger, Lester Crudele | 2021-10-19 |
| 11100994 | Content addressable memory device having electrically floating body transistor | Jin-Woo Han, Yuniarto Widjaja | 2021-08-24 |
| 11010294 | MRAM noise mitigation for write operations with simultaneous background operations | Neal Berger, Lester Crudele | 2021-05-18 |
| 10991697 | NAND string utilizing floating body memory cell | Jin-Woo Han, Yuniarto Widjaja | 2021-04-27 |
| 10991410 | Bi-polar write scheme | Neal Berger, Kadriye Deniz Bozdag | 2021-04-27 |
| 10990465 | MRAM noise mitigation for background operations by delaying verify timing | Neal Berger, Lester Crudele | 2021-04-27 |