Issued Patents All Time
Showing 25 most recent of 72 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12094526 | Memory device comprising electrically floating body transistor | Jin-Woo Han, Yuniarto Widjaja | 2024-09-17 |
| 11941299 | MRAM access coordination systems and methods via pipeline in parallel | Benjamin Louie, Lester Crudele | 2024-03-26 |
| 11715515 | Memory device comprising electrically floating body transistor | Jin-Woo Han, Yuniarto Widjaja | 2023-08-01 |
| 11586553 | Error cache system with coarse and fine segments for power optimization | Susmita Karmakar, TaeJin Pyon, Kuk-Hwan Kim | 2023-02-21 |
| 11580014 | Heuristics for selecting subsegments for entry in and entry out operations in an error cache system with coarse and fine grain segments | Susmita Karmakar, TaeJin Pyon, Kuk-Hwan Kim | 2023-02-14 |
| 11423965 | Word line decoder memory architecture | Susmita Karmakar, Benjamin Louie | 2022-08-23 |
| 11386010 | Circuit engine for managing memory meta-stability | Benjamin Louie, Lester Crudele | 2022-07-12 |
| 11334288 | MRAM access coordination systems and methods with a plurality of pipelines | Benjamin Louie, Lester Crudele | 2022-05-17 |
| 11250905 | Memory device comprising electrically floating body transistor | Jin-Woo Han, Yuniarto Widjaja | 2022-02-15 |
| 11151042 | Error cache segmentation for power reduction | Benjamin Louie, Lester Crudele | 2021-10-19 |
| 11119936 | Error cache system with coarse and fine segments for power optimization | Susmita Karmakar, TaeJin Pyon, Kuk-Hwan Kim | 2021-09-14 |
| 11119910 | Heuristics for selecting subsegments for entry in and entry out operations in an error cache system with coarse and fine grain segments | Susmita Karmakar, TaeJin Pyon, Kuk-Hwan Kim | 2021-09-14 |
| 11048633 | Determining an inactive memory bank during an idle memory cycle to prevent error cache overflow | Susmita Karmakar | 2021-06-29 |
| 11010294 | MRAM noise mitigation for write operations with simultaneous background operations | Benjamin Louie, Lester Crudele | 2021-05-18 |
| 10991410 | Bi-polar write scheme | Benjamin Louie, Kadriye Deniz Bozdag | 2021-04-27 |
| 10990465 | MRAM noise mitigation for background operations by delaying verify timing | Benjamin Louie, Lester Crudele | 2021-04-27 |
| 10930332 | Memory array with individually trimmable sense amplifiers | Susmita Karmakar, Mourad El Baraji, Benjamin Louie | 2021-02-23 |
| 10923183 | Memory device comprising electrically floating body transistor | Jin-Woo Han, Yuniarto Widjaja | 2021-02-16 |
| 10891997 | Memory array with horizontal source line and a virtual source line | Mourad El Baraji, Lester Crudele, Benjamin Louie | 2021-01-12 |
| 10818331 | Multi-chip module for MRAM devices with levels of dynamic redundancy registers | Benjamin Louie | 2020-10-27 |
| 10803949 | Master slave level shift latch for word line decoder memory architecture | Susmita Karmakar, Benjamin Louie | 2020-10-13 |
| 10699761 | Word line decoder memory architecture | Susmita Karmakar, Benjamin Louie | 2020-06-30 |
| 10656994 | Over-voltage write operation of tunnel magnet-resistance (“TMR”) memory device and correcting failure bits therefrom by using on-the-fly bit failure detection and bit redundancy remapping techniques | Benjamin Louie, Mourad El-Baraji, Lester Crudele | 2020-05-19 |
| 10628316 | Memory device with a plurality of memory banks where each memory bank is associated with a corresponding memory instruction pipeline and a dynamic redundancy register | Benjamin Louie, Mourad El-Baraji, Lester Crudele, Daniel L. Hillman | 2020-04-21 |
| 10580482 | Memory device comprising electrically floating body transistor | Jin-Woo Han, Yuniarto Widjaja | 2020-03-03 |