TP

TaeJin Pyon

SM Spin Memory: 3 patents #29 of 49Top 60%
I( Integrated Silicon Solution, (Cayman): 2 patents #25 of 36Top 70%
Oracle: 1 patents #8,282 of 14,854Top 60%
Overall (All Time): #805,555 of 4,157,543Top 20%
6
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
11586553 Error cache system with coarse and fine segments for power optimization Neal Berger, Susmita Karmakar, Kuk-Hwan Kim 2023-02-21
11580014 Heuristics for selecting subsegments for entry in and entry out operations in an error cache system with coarse and fine grain segments Neal Berger, Susmita Karmakar, Kuk-Hwan Kim 2023-02-14
11119910 Heuristics for selecting subsegments for entry in and entry out operations in an error cache system with coarse and fine grain segments Neal Berger, Susmita Karmakar, Kuk-Hwan Kim 2021-09-14
11119936 Error cache system with coarse and fine segments for power optimization Neal Berger, Susmita Karmakar, Kuk-Hwan Kim 2021-09-14
10546625 Method of optimizing write voltage based on error buffer occupancy Neal Berger, Benjamin Louie, Kuk-Hwan Kim 2020-01-28
9281028 Method and circuit for glitch reduction in memory read latch circuit Yong Qin, Thu Nguyen 2016-03-08