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USPTO Patent Rankings Data through Dec 31, 2025
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TaeJin Pyon — 6 Patents

SMSpin Memory: 3 patents #29 of 49Top 60%
I(Integrated Silicon Solution, (Cayman): 2 patents #25 of 36Top 70%
Oracle: 1 patents #8,339 of 14,854Top 60%
San Jose, CA: #9,609 of 32,062 inventorsTop 30%
California: #94,478 of 386,348 inventorsTop 25%
Overall (All Time): #779,687 of 4,157,543Top 20%
6 Patents All Time
TaeJin Pyon has been granted 6 US patents while listed as an inventor at Spin Memory. The first was granted in 2016 and the most recent in February 2023. TaeJin Pyon ranks #779,687 of 4,157,543 US inventors in our database (top 18.8%). Patent records list TaeJin Pyon in San Jose, CA, US.

Issued Patents All Time

Showing 1–6 of 6 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
11586553 Error cache system with coarse and fine segments for power optimization Neal Berger, Susmita Karmakar, Kuk-Hwan Kim 2023-02-21
11580014 Heuristics for selecting subsegments for entry in and entry out operations in an error cache system with coarse and fine grain segments Neal Berger, Susmita Karmakar, Kuk-Hwan Kim 2023-02-14
11119910 Heuristics for selecting subsegments for entry in and entry out operations in an error cache system with coarse and fine grain segments Neal Berger, Susmita Karmakar, Kuk-Hwan Kim 2021-09-14
11119936 Error cache system with coarse and fine segments for power optimization Neal Berger, Susmita Karmakar, Kuk-Hwan Kim 2021-09-14
10546625 Method of optimizing write voltage based on error buffer occupancy Neal Berger, Benjamin Louie, Kuk-Hwan Kim 2020-01-28
9281028 Method and circuit for glitch reduction in memory read latch circuit Yong Qin, Thu Nguyen 2016-03-08 $37,378,000