Issued Patents All Time
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11586553 | Error cache system with coarse and fine segments for power optimization | Neal Berger, TaeJin Pyon, Kuk-Hwan Kim | 2023-02-21 |
| 11580014 | Heuristics for selecting subsegments for entry in and entry out operations in an error cache system with coarse and fine grain segments | Neal Berger, TaeJin Pyon, Kuk-Hwan Kim | 2023-02-14 |
| 11423965 | Word line decoder memory architecture | Neal Berger, Benjamin Louie | 2022-08-23 |
| 11119910 | Heuristics for selecting subsegments for entry in and entry out operations in an error cache system with coarse and fine grain segments | Neal Berger, TaeJin Pyon, Kuk-Hwan Kim | 2021-09-14 |
| 11119936 | Error cache system with coarse and fine segments for power optimization | Neal Berger, TaeJin Pyon, Kuk-Hwan Kim | 2021-09-14 |
| 11048633 | Determining an inactive memory bank during an idle memory cycle to prevent error cache overflow | Neal Berger | 2021-06-29 |
| 10930332 | Memory array with individually trimmable sense amplifiers | Neal Berger, Mourad El Baraji, Benjamin Louie | 2021-02-23 |
| 10803949 | Master slave level shift latch for word line decoder memory architecture | Neal Berger, Benjamin Louie | 2020-10-13 |
| 10699761 | Word line decoder memory architecture | Neal Berger, Benjamin Louie | 2020-06-30 |
| 10360962 | Memory array with individually trimmable sense amplifiers | Neal Berger, Mourad El Baraji, Benjamin Louie | 2019-07-23 |
| 7116088 | High voltage shunt regulator for flash memory | Hieu Van Tran, Thuan Vu | 2006-10-03 |