Issued Patents All Time
Showing 25 most recent of 35 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11941299 | MRAM access coordination systems and methods via pipeline in parallel | Benjamin Louie, Neal Berger | 2024-03-26 |
| 11386010 | Circuit engine for managing memory meta-stability | Neal Berger, Benjamin Louie | 2022-07-12 |
| 11334288 | MRAM access coordination systems and methods with a plurality of pipelines | Benjamin Louie, Neal Berger | 2022-05-17 |
| 11151042 | Error cache segmentation for power reduction | Benjamin Louie, Neal Berger | 2021-10-19 |
| 11010294 | MRAM noise mitigation for write operations with simultaneous background operations | Benjamin Louie, Neal Berger | 2021-05-18 |
| 10990465 | MRAM noise mitigation for background operations by delaying verify timing | Benjamin Louie, Neal Berger | 2021-04-27 |
| 10891997 | Memory array with horizontal source line and a virtual source line | Neal Berger, Mourad El Baraji, Benjamin Louie | 2021-01-12 |
| 10656994 | Over-voltage write operation of tunnel magnet-resistance (“TMR”) memory device and correcting failure bits therefrom by using on-the-fly bit failure detection and bit redundancy remapping techniques | Neal Berger, Benjamin Louie, Mourad El-Baraji | 2020-05-19 |
| 10628316 | Memory device with a plurality of memory banks where each memory bank is associated with a corresponding memory instruction pipeline and a dynamic redundancy register | Neal Berger, Benjamin Louie, Mourad El-Baraji, Daniel L. Hillman | 2020-04-21 |
| 10546624 | Multi-port random access memory | Mourad El-Baraji, Neal Berger, Benjamin Louie | 2020-01-28 |
| 10529439 | On-the-fly bit failure detection and bit redundancy remapping techniques to correct for fixed bit defects | Neal Berger, Benjamin Louie, Mourad El-Baraji | 2020-01-07 |
| 10489245 | Forcing stuck bits, waterfall bits, shunt bits and low TMR bits to short during testing and using on-the-fly bit failure detection and bit redundancy remapping techniques to correct them | Neal Berger, Benjamin Louie, Mourad El-Baraji | 2019-11-26 |
| 10481976 | Forcing bits as bad to widen the window between the distributions of acceptable high and low resistive bits thereby lowering the margin and increasing the speed of the sense amplifiers | Neal Berger, Benjamin Louie, Mourad El-Baraji | 2019-11-19 |
| 10460781 | Memory device with a dual Y-multiplexer structure for performing two simultaneous operations on the same row of a memory bank | Neal Berger, Benjamin Louie, Mourad El-Baraji, Daniel L. Hillman | 2019-10-29 |
| 10446210 | Memory instruction pipeline with a pre-read stage for a write operation for reducing power consumption in a memory device that uses dynamic redundancy registers | Neal Berger, Benjamin Louie, Mourad El-Baraji, Daniel L. Hillman | 2019-10-15 |
| 10437723 | Method of flushing the contents of a dynamic redundancy register to a secure storage area during a power down in a memory device | Neal Berger, Benjamin Louie, Mourad El-Baraji, Daniel L. Hillman | 2019-10-08 |
| 10437491 | Method of processing incomplete memory operations in a memory device during a power up sequence and a power down sequence using a dynamic redundancy register | Neal Berger, Benjamin Louie, Mourad El-Baraji, Daniel L. Hillman | 2019-10-08 |
| 10424393 | Method of reading data from a memory device using multiple levels of dynamic redundancy registers | Mourad El Baraji, Neal Berger, Benjamin Louie, Daniel L. Hillman, Barry A. Hoberman | 2019-09-24 |
| 10395712 | Memory array with horizontal source line and sacrificial bitline per virtual source | Neal Berger, Mourad El Baraji, Benjamin Louie | 2019-08-27 |
| 10395711 | Perpendicular source and bit lines for an MRAM array | Neal Berger, Benjamin Louie, Mourad El Baraji | 2019-08-27 |
| 10366774 | Device with dynamic redundancy registers | Mourad El Baraji, Neal Berger, Benjamin Louie, Daniel L. Hillman, Barry A. Hoberman | 2019-07-30 |
| 10366775 | Memory device using levels of dynamic redundancy registers for writing a data word that failed a write operation | Mourad El-Baraji, Neal Berger, Benjamin Louie, Daniel L. Hillman, Barry A. Hoberman | 2019-07-30 |
| 10360964 | Method of writing contents in memory during a power up sequence using a dynamic redundancy register in a memory device | Neal Berger, Benjamin Louie, Mourad El-Baraji, Daniel L. Hillman | 2019-07-23 |
| 10192601 | Memory instruction pipeline with an additional write stage in a memory device that uses dynamic redundancy registers | Neal Berger, Benjamin Louie, Mourad El-Baraji, Daniel L. Hillman | 2019-01-29 |
| 10192602 | Smart cache design to prevent overflow for a memory device with a dynamic redundancy register | Neal Berger, Benjamin Louie, Mourad El-Baraji, Daniel L. Hillman | 2019-01-29 |