Issued Patents All Time
Showing 25 most recent of 74 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9552311 | Method for assigning addresses to memory devices | Robert Norman | 2017-01-24 |
| 9213630 | Non-volatile memory devices and control and operation thereof | Benjamin Louie | 2015-12-15 |
| 8745355 | Method for assigning addresses to memory devices | Robert Norman | 2014-06-03 |
| 8145832 | Non-volatile memory devices and control and operation thereof | Benjamin Louie | 2012-03-27 |
| 7962784 | Repairable block redundancy scheme | Benjamin Louie | 2011-06-14 |
| 7911872 | Column/row redundancy architecture using latches programmed from a look up table | Benjamin Louie | 2011-03-22 |
| 7908427 | Non-volatile memory devices and control and operation thereof | Benjamin Louie | 2011-03-15 |
| 7746629 | Method and system for coupling a laptop or other portable or hand-held device to a docking system using an Ethernet interface | Simon Assouad | 2010-06-29 |
| 7546440 | Non-volatile memory devices and control and operation thereof | Benjamin Louie | 2009-06-09 |
| 7539896 | Repairable block redundancy scheme | Benjamin Louie | 2009-05-26 |
| 7505357 | Column/row redundancy architecture using latches programmed from a look up table | Benjamin Louie | 2009-03-17 |
| 7444458 | Method for assigning addresses to memory devices | Robert Norman | 2008-10-28 |
| 7366027 | Method and apparatus for erasing memory | Tz-Yi Liu | 2008-04-29 |
| 7251187 | Memory system, method and predecoding circuit operable in different modes for selectively accessing multiple blocks of memory cells for simultaneous writing or erasure | Christophe J. Chevallier, Mathew L. Adsitt | 2007-07-31 |
| 7215571 | Method for reducing drain disturb in programming | Andrei Mihnea | 2007-05-08 |
| 7159141 | Repairable block redundancy scheme | Benjamin Louie | 2007-01-02 |
| 7154781 | Contiguous block addressing scheme | Benjamin Louie | 2006-12-26 |
| 7154780 | Contiguous block addressing scheme | Benjamin Louie | 2006-12-26 |
| 7154782 | Contiguous block addressing scheme | Benjamin Louie | 2006-12-26 |
| 7133323 | Memory system, method and predecoding circuit operable in different modes for selectively accessing multiple blocks of memory cells for simultaneous writing or erasure | Christophe J. Chevallier, Mathew L. Adsitt | 2006-11-07 |
| 7130239 | Memory system, method and predecoding circuit operable in different modes for selectively accessing multiple blocks of memory cells for simultaneous writing or erasure | Christophe J. Chevallier, Mathew L. Adsitt | 2006-10-31 |
| 7123512 | Contiguous block addressing scheme | Benjamin Louie | 2006-10-17 |
| 7120068 | Column/row redundancy architecture using latches programmed from a look up table | Benjamin Louie | 2006-10-10 |
| 6965923 | System and method for assigning addresses to memory devices | Robert Norman | 2005-11-15 |
| 6961805 | Memory system, method and predecoding circuit operable in different modes for selectively accessing multiple blocks of memory cells for simultaneous reading writing or erasure | Christophe J. Chevallier, Mathew L. Adsitt | 2005-11-01 |