Issued Patents All Time
Showing 26–50 of 130 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10978455 | Memory device having electrically floating body transistor | Yuniarto Widjaja, Jin-Woo Han | 2021-04-13 |
| 10930332 | Memory array with individually trimmable sense amplifiers | Susmita Karmakar, Neal Berger, Mourad El Baraji | 2021-02-23 |
| 10891997 | Memory array with horizontal source line and a virtual source line | Neal Berger, Mourad El Baraji, Lester Crudele | 2021-01-12 |
| 10839905 | Content addressable memory device having electrically floating body transistor | Jin-Woo Han, Yuniarto Widjaja | 2020-11-17 |
| 10818331 | Multi-chip module for MRAM devices with levels of dynamic redundancy registers | Neal Berger | 2020-10-27 |
| 10803949 | Master slave level shift latch for word line decoder memory architecture | Neal Berger, Susmita Karmakar | 2020-10-13 |
| 10797055 | Memory cell comprising first and second transistors and methods of operating | Yuniarto Widjaja, Jin-Woo Han | 2020-10-06 |
| 10783952 | Systems and methods for reducing standby power in floating body memory devices | Yuniarto Widjaja | 2020-09-22 |
| 10699761 | Word line decoder memory architecture | Neal Berger, Susmita Karmakar | 2020-06-30 |
| 10656994 | Over-voltage write operation of tunnel magnet-resistance (“TMR”) memory device and correcting failure bits therefrom by using on-the-fly bit failure detection and bit redundancy remapping techniques | Neal Berger, Mourad El-Baraji, Lester Crudele | 2020-05-19 |
| 10629599 | Memory device having electrically floating body transistor | Yuniarto Widjaja, Jin-Woo Han | 2020-04-21 |
| 10628316 | Memory device with a plurality of memory banks where each memory bank is associated with a corresponding memory instruction pipeline and a dynamic redundancy register | Neal Berger, Mourad El-Baraji, Lester Crudele, Daniel L. Hillman | 2020-04-21 |
| 10546625 | Method of optimizing write voltage based on error buffer occupancy | Neal Berger, Kuk-Hwan Kim, TaeJin Pyon | 2020-01-28 |
| 10546624 | Multi-port random access memory | Mourad El-Baraji, Neal Berger, Lester Crudele | 2020-01-28 |
| 10546860 | NAND string utilizing floating body memory cell | Jin-Woo Han, Yuniarto Widjaja | 2020-01-28 |
| 10529439 | On-the-fly bit failure detection and bit redundancy remapping techniques to correct for fixed bit defects | Neal Berger, Mourad El-Baraji, Lester Crudele | 2020-01-07 |
| 10504585 | Scalable floating body memory cell for memory compilers and method of using floating body memories with memory compilers | Yuniarto Widjaja, Zvi Or-Bach | 2019-12-10 |
| 10489245 | Forcing stuck bits, waterfall bits, shunt bits and low TMR bits to short during testing and using on-the-fly bit failure detection and bit redundancy remapping techniques to correct them | Neal Berger, Mourad El-Baraji, Lester Crudele | 2019-11-26 |
| 10481976 | Forcing bits as bad to widen the window between the distributions of acceptable high and low resistive bits thereby lowering the margin and increasing the speed of the sense amplifiers | Neal Berger, Mourad El-Baraji, Lester Crudele | 2019-11-19 |
| 10460781 | Memory device with a dual Y-multiplexer structure for performing two simultaneous operations on the same row of a memory bank | Neal Berger, Mourad El-Baraji, Lester Crudele, Daniel L. Hillman | 2019-10-29 |
| 10446210 | Memory instruction pipeline with a pre-read stage for a write operation for reducing power consumption in a memory device that uses dynamic redundancy registers | Neal Berger, Mourad El-Baraji, Lester Crudele, Daniel L. Hillman | 2019-10-15 |
| 10437491 | Method of processing incomplete memory operations in a memory device during a power up sequence and a power down sequence using a dynamic redundancy register | Neal Berger, Mourad El-Baraji, Lester Crudele, Daniel L. Hillman | 2019-10-08 |
| 10437723 | Method of flushing the contents of a dynamic redundancy register to a secure storage area during a power down in a memory device | Neal Berger, Mourad El-Baraji, Lester Crudele, Daniel L. Hillman | 2019-10-08 |
| 10424393 | Method of reading data from a memory device using multiple levels of dynamic redundancy registers | Mourad El Baraji, Neal Berger, Lester Crudele, Daniel L. Hillman, Barry A. Hoberman | 2019-09-24 |
| 10395711 | Perpendicular source and bit lines for an MRAM array | Neal Berger, Mourad El Baraji, Lester Crudele | 2019-08-27 |