Issued Patents All Time
Showing 51–75 of 130 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10395712 | Memory array with horizontal source line and sacrificial bitline per virtual source | Neal Berger, Mourad El Baraji, Lester Crudele | 2019-08-27 |
| 10373685 | Content addressable memory device having electrically floating body transistor | Jin-Woo Han, Yuniarto Widjaja | 2019-08-06 |
| 10366774 | Device with dynamic redundancy registers | Mourad El Baraji, Neal Berger, Lester Crudele, Daniel L. Hillman, Barry A. Hoberman | 2019-07-30 |
| 10366775 | Memory device using levels of dynamic redundancy registers for writing a data word that failed a write operation | Mourad El-Baraji, Neal Berger, Lester Crudele, Daniel L. Hillman, Barry A. Hoberman | 2019-07-30 |
| 10360964 | Method of writing contents in memory during a power up sequence using a dynamic redundancy register in a memory device | Neal Berger, Mourad El-Baraji, Lester Crudele, Daniel L. Hillman | 2019-07-23 |
| 10360962 | Memory array with individually trimmable sense amplifiers | Susmita Karmakar, Neal Berger, Mourad El Baraji | 2019-07-23 |
| 10354718 | Systems and methods for reducing standby power in floating body memory devices | Yuniarto Widjaja | 2019-07-16 |
| 10332603 | Access line management in a memory device | Ali Mohammadzadeh, Aaron Yip | 2019-06-25 |
| 10236075 | Predicting tunnel barrier endurance using redundant memory structures | Kuk-Hwan Kim, Peter Cuevas, Amitay Levi | 2019-03-19 |
| 10192601 | Memory instruction pipeline with an additional write stage in a memory device that uses dynamic redundancy registers | Neal Berger, Mourad El-Baraji, Lester Crudele, Daniel L. Hillman | 2019-01-29 |
| 10192602 | Smart cache design to prevent overflow for a memory device with a dynamic redundancy register | Neal Berger, Mourad El-Baraji, Lester Crudele, Daniel L. Hillman | 2019-01-29 |
| 10192872 | Memory device having electrically floating body transistor | Yuniarto Widjaja, Jin-Woo Han | 2019-01-29 |
| 10181471 | Memory cell comprising first and second transistors and methods of operating | Yuniarto Widjaja, Jin-Woo Han | 2019-01-15 |
| 10157663 | Systems and methods for reducing standby power in floating body memory devices | Yuniarto Widjaja | 2018-12-18 |
| 10115446 | Spin transfer torque MRAM device with error buffer | Neal Berger | 2018-10-30 |
| 10103148 | NAND string utilizing floating body memory cell | Jin-Woo Han, Yuniarto Widjaja | 2018-10-16 |
| 10026479 | Content addressable memory device having electrically floating body transistor | Jin-Woo Han, Yuniarto Widjaja | 2018-07-17 |
| 9947387 | Systems and methods for reducing standby power in floating body memory devices | Yuniarto Widjaja | 2018-04-17 |
| 9905564 | Memory cell comprising first and second transistors and methods of operating | Yuniarto Widjaja, Jin-Woo Han | 2018-02-27 |
| 9893067 | Memory device having electrically floating body transistor | Yuniarto Widjaja, Jin-Woo Han | 2018-02-13 |
| 9875802 | Access line management in a memory device | Ali Mohammadzadeh, Aaron Yip | 2018-01-23 |
| 9865332 | Scalable floating body memory cell for memory compilers and method of using floating body memories with memory compilers | Yuniarto Widjaja, Zvi Or-Bach | 2018-01-09 |
| 9704578 | NAND string utilizing floating body memory cell | Jin-Woo Han, Yuniarto Widjaja | 2017-07-11 |
| 9576962 | Memory device having electrically floating body transistor | Yuniarto Widjaja, Jin-Woo Han | 2017-02-21 |
| 9536595 | Systems and methods for reducing standby power in floating body memory devices | Yuniarto Widjaja | 2017-01-03 |