Issued Patents All Time
Showing 25 most recent of 29 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12356614 | Memory array having connections going through control gates | Toru Tanzawa, Tamotsu Murakoshi | 2025-07-08 |
| 12340845 | Split block array for 3D NAND memory | Chang Wan Ha, Hoon Koh, Richard M. Gularte, Liu Liu, David S. Meyaard +1 more | 2025-06-24 |
| 12148802 | Vertical string driver with channel field management structure | Dong Ji, Guangyu Huang | 2024-11-19 |
| 12120878 | Block-to-block isolation and deep contact using pillars in a memory array | Brian Cleereman, Srivardhan Gowda, Jui-Yen Lin, Liu Liu, Krishna K. Parat +2 more | 2024-10-15 |
| 12089412 | Vertical string driver with extended gate junction structure | Dong Ji, Guangyu Huang | 2024-09-10 |
| 11653496 | Asymmetric junctions of high voltage transistor in NAND flash memory | Chang Wan Ha, Chuan Lin, Zengtao T. Liu, Binh Ngo, Soo Yong Park | 2023-05-16 |
| 11424256 | Transistors, semiconductor constructions, and methods of forming semiconductor constructions | Andrew Bicksler, Roland J. Awusie | 2022-08-23 |
| 11398489 | Memory array having connections going through control gates | Toru Tanzawa, Tamotsu Murakoshi | 2022-07-26 |
| 11393716 | Devices including stair step structures, and related apparatuses and memory devices | Chang Wan Ha, Graham R. Wolstenholme | 2022-07-19 |
| 10804280 | Memory device with vertical string drivers | Khaled Hasnat, Prashant Majhi | 2020-10-13 |
| 10770470 | Memory array having connections going through control gates | Toru Tanzawa, Tamotsu Murakoshi | 2020-09-08 |
| 10748811 | Memory devices and related methods | Chang Wan Ha, Graham R. Wolstenholme | 2020-08-18 |
| 10593624 | Three dimensional storage cell array with highly dense and scalable word line design approach | Aaron Yip, Mark A. Helm, Yongna Li | 2020-03-17 |
| 10515973 | Wordline bridge in a 3D memory array | Owen W. Jungroth, David S. Meyaard, Khaled Hasnat | 2019-12-24 |
| 10497707 | Semiconductor constructions which include metal-containing gate portions and semiconductor-containing gate portions | Andrew Bicksler, Roland J. Awusie | 2019-12-03 |
| 10269626 | Stair step formation using at least two masks | Chang Wan Ha, Graham R. Wolstenholme | 2019-04-23 |
| 10043751 | Three dimensional storage cell array with highly dense and scalable word line design approach | Aaron Yip, Mark A. Helm, Yongna Li | 2018-08-07 |
| 9870941 | Stair step formation using at least two masks | Chang Wan Ha, Graham R. Wolstenholme | 2018-01-16 |
| 9865357 | Performing read operations on a memory device | Pranav Kalavade, Aaron Yip, Shantanu R. Rajwade | 2018-01-09 |
| 9613978 | Methods of forming semiconductor constructions | Andrew Bicksler, Roland J. Awusie | 2017-04-04 |
| 9595533 | Memory array having connections going through control gates | Toru Tanzawa, Tamotsu Murakoshi | 2017-03-14 |
| 9557376 | Apparatuses and methods for die seal crack detection | Charles H. Dennison, Kenneth W. Marr, Philip J. Ireland | 2017-01-31 |
| 9508591 | Stair step formation using at least two masks | Chang Wan Ha, Graham R. Wolstenholme | 2016-11-29 |
| 9287184 | Apparatuses and methods for die seal crack detection | Charles H. Dennison, Kenneth W. Marr, Philip J. Ireland | 2016-03-15 |
| 9219070 | 3-D memory arrays | Brian Cleereman, Khaled Hasnat | 2015-12-22 |