Issued Patents All Time
Showing 25 most recent of 34 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12394492 | Memory cell sensing circuit with adjusted bias from pre-boost operation | Bayan Nasri, Tzu-Ning Fang, Rezaul Haque, Dhanashree Kulkarni, Narayanan Ramanan +4 more | 2025-08-19 |
| 12394497 | Efficient bitline stabilization for program inhibit in NAND arrays | Tarek Ahmed Ameen Beshari, Ahsanur Rahman, Sagar Upadhyay, Pratyush Chandrapati | 2025-08-19 |
| 12334152 | Simultaneous programming of multiple sub-blocks in NAND memory structures | Ali Khakifirooz, Pranav Kalavade, Tarek Ahmed Ameen Beshari | 2025-06-17 |
| 12322455 | Program verify process having placement aware pre-program verify (PPV) bucket size modulation | Tarek Ahmed Ameen Beshari, Matin Amani, Narayanan Ramanan, Arun Thathachary | 2025-06-03 |
| 12243590 | Method and apparatus for improving write uniformity in a memory device | Christian Mion, Pranav Kalavade, Rohit S. Shenoy, Xin Sun, Kristopher H. Gaewsky | 2025-03-04 |
| 12237023 | Dynamic detection and dynamic adjustment of sub-threshold swing in a memory cell sensing circuit | Tarek Ahmed Ameen Beshari, Matin Amani, Narayanan Ramanan | 2025-02-25 |
| 12224019 | Cache processes with adaptive dynamic start voltage calculation for memory devices | Xiang Yang, Ali Khakifirooz, Pranav Kalavade | 2025-02-11 |
| 12211563 | Dynamic gate steps for last-level programming to improve write performance | Sagar Upadhyay, Archana Tankasala, Aliasgar S. Madraswala | 2025-01-28 |
| 12189955 | Skip program verify for dynamic start voltage sampling | Archana Tankasala, Sagar Upadhyay, Aliasgar S. Madraswala | 2025-01-07 |
| 12051472 | Solid state drive (SSD) with in-flight erasure iteration suspension | Justin R. Dayacap, Kyung Jean Yoon, Ali Khakifirooz, David J. Pelster, Yogesh B. Wakchaure +1 more | 2024-07-30 |
| 11721396 | Configuration of a memory device for programming memory cells | Violante Moschiano, Purval S. Sule, Han Liu, Andrea D'Alessandro, Pranav Kalavade +1 more | 2023-08-08 |
| 11698725 | Apparatuses and methods for concurrently accessing multiple memory planes of a memory during a memory access operation | Pranav Kalavade, Toru Tanzawa | 2023-07-11 |
| 11182074 | Apparatuses and methods for concurrently accessing multiple memory planes of a memory during a memory access operation | Pranav Kalavade, Toru Tanzawa | 2021-11-23 |
| 11139036 | Using variable voltages to discharge electrons from a memory array during verify recovery operations | Tarek Ahmed Ameen Beshari, Pranav Chava, Sagar Upadhyay | 2021-10-05 |
| 11094386 | Device, system, and method to verify data programming of a multi-level cell memory based on one of temperature, pressure, wear condition or relative position of the memory cell | Xiang Yang, Tarek Ahmed Ameen Beshari, Narayanan Ramanan, Arun Thathachary, Matin Amani | 2021-08-17 |
| 11056203 | Boosted bitlines for storage cell programmed state verification in a memory array | Xiang Yang, Pranav Kalavade, Ali Khakifirooz, Sagar Upadhyay | 2021-07-06 |
| 11004524 | SSD having a parallelized, multi-level program voltage verification | Xiang Yang, Ali Khakifirooz, Tarek Ahmed Ameen Beshari | 2021-05-11 |
| 10777277 | Configuration of a memory device for programming memory cells | Violante Moschiano, Purval S. Sule, Han Liu, Andrea D'Alessandro, Pranav Kalavade +1 more | 2020-09-15 |
| 10714186 | Method and apparatus for dynamically determining start program voltages for a memory device | Purval S. Sule, Aliasgar S. Madraswala, Trupti Bemalkhedkar, Leonard Aaron Turcios, Kristopher H. Gaewsky | 2020-07-14 |
| 10658053 | Ramping inhibit voltage during memory programming | Pranav Kalavade, Neal R. Mielke, Krishna K. Parat, Shyam Sunder Raghunathan | 2020-05-19 |
| 10482974 | Operation of a memory device during programming | Violante Moschiano, Purval S. Sule, Han Liu, Andrea D'Alessandro, Pranav Kalavade +1 more | 2019-11-19 |
| 10453535 | Segmented erase in memory | Akira Goda, Pranav Kalavade, Krishna K. Parat, Hiroyuki Sanda | 2019-10-22 |
| 10430114 | Buffer operations in memory | Pranav Kalavade | 2019-10-01 |
| 10379738 | Apparatuses and methods for concurrently accessing multiple memory planes of a memory during a memory access operation | Pranav Kalavade, Toru Tanzawa | 2019-08-13 |
| 10289313 | Method and apparatus for improving sequential reading in NAND flash | Han-Din Liu, Pranav Kalavade | 2019-05-14 |