Issued Patents All Time
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12394497 | Efficient bitline stabilization for program inhibit in NAND arrays | Tarek Ahmed Ameen Beshari, Shantanu R. Rajwade, Sagar Upadhyay, Pratyush Chandrapati | 2025-08-19 |
| 12394492 | Memory cell sensing circuit with adjusted bias from pre-boost operation | Shantanu R. Rajwade, Bayan Nasri, Tzu-Ning Fang, Rezaul Haque, Dhanashree Kulkarni +4 more | 2025-08-19 |
| 12340845 | Split block array for 3D NAND memory | Chang Wan Ha, Deepak Thimmegowda, Hoon Koh, Richard M. Gularte, Liu Liu +1 more | 2025-06-24 |
| 12334136 | Independent multi-page read operation enhancement technology | Naveen Prabhu, Aliasgar S. Madraswala, Bharat Pathak, Binh Ngo, Netra Mahuli | 2025-06-17 |
| 12315567 | Grouped global wordline driver with shared bias scheme | Chang Wan Ha, Binh Ngo, Radhika Chinnammagari, Sagar Upadhyay | 2025-05-27 |
| 7551489 | Multi-level memory cell sensing | Kerry D. Tedrow, Dung C. Nguyen, Bo Li, Rezaul Haque, Saad Monasa +1 more | 2009-06-23 |
| 7525840 | Memory array with pseudo single bit memory cell and method | Rezaul Haque, Kerry D. Tedrow | 2009-04-28 |
| 7272041 | Memory array with pseudo single bit memory cell and method | Rezaul Haque, Kerry D. Tedrow | 2007-09-18 |