Issued Patents All Time
Showing 25 most recent of 63 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10942873 | Memory tile access and selection patterns | Hernan A. Castro, Jack Chinho Wu | 2021-03-09 |
| 10748613 | Memory sense amplifiers and memory verification methods | Makoto Kitagawa | 2020-08-18 |
| 10387338 | Memory tile access and selection patterns | Hernan A. Castro, Jack Chinho Wu | 2019-08-20 |
| 10147487 | Memory sense amplifiers and memory verification methods | Makoto Kitagawa | 2018-12-04 |
| 9959220 | Memory tile access and selection patterns | Hernan A. Castro, Jack Chinho Wu | 2018-05-01 |
| 9799398 | Memory cell verification circuits, memory cell sense circuits and memory cell verification methods | Makoto Kitagawa | 2017-10-24 |
| 9626292 | Memory tile access and selection patterns | Hernan A. Castro, Jack Chinho Wu | 2017-04-18 |
| 9564181 | Memory device comprising double cascode sense amplifiers | — | 2017-02-07 |
| 9437288 | Dual mode clock and data scheme for memory programming | — | 2016-09-06 |
| 9406362 | Memory tile access and selection patterns | Hernan A. Castro, Jack Chinho Wu | 2016-08-02 |
| 9311999 | Memory sense amplifiers and memory verification methods | Makoto Kitagawa | 2016-04-12 |
| 8804411 | Dual mode clock and data scheme for memory programming | — | 2014-08-12 |
| 8259488 | Phase-change memory temperature sensitive detector | Jahanshir J. Javanifard | 2012-09-04 |
| 8176232 | Dedicated interface to factory program phase-change memories | Nicholas Hendrickson | 2012-05-08 |
| 8059468 | Switched bitline VTH sensing for non-volatile memories | Nicholas Hendrickson | 2011-11-15 |
| 7551489 | Multi-level memory cell sensing | Dung C. Nguyen, Bo Li, Rezaul Haque, Ahsanur Rahman, Saad Monasa +1 more | 2009-06-23 |
| 7525865 | Control circuit for refreshing voltages in a non-volatile memory during a standby mode and a method thereof | Bharat V. Chauhan, Gerald Barkley, Balaji Bhathey Sivakumar | 2009-04-28 |
| 7525840 | Memory array with pseudo single bit memory cell and method | Ahsanur Rahman, Rezaul Haque | 2009-04-28 |
| 7319616 | Negatively biasing deselected memory cells | Rajesh Sundaram, Jahanshir J. Javanifard, Priya Walimbe, Tom H. Ly, Raymond W. Zeng | 2008-01-15 |
| 7313019 | Step voltage generation | Hari Giduturi | 2007-12-25 |
| 7272041 | Memory array with pseudo single bit memory cell and method | Ahsanur Rahman, Rezaul Haque | 2007-09-18 |
| 7176751 | Voltage reference apparatus, method, and system | Hari Giduturi | 2007-02-13 |
| 7139205 | Apparatuses and methods for pre-charging intermediate nodes for high-speed wordline | Matthew Goldman, Gerald Barkley, Alec W. Smidt | 2006-11-21 |
| 7116597 | High precision reference devices and methods | Matthew Goldman, Balaji Srinivasan, Paul D. Ruby | 2006-10-03 |
| 6944065 | Method, apparatus, and system to enhance negative voltage switching | Rajesh Sundaram | 2005-09-13 |