Issued Patents All Time
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12394497 | Efficient bitline stabilization for program inhibit in NAND arrays | Shantanu R. Rajwade, Ahsanur Rahman, Sagar Upadhyay, Pratyush Chandrapati | 2025-08-19 |
| 12334152 | Simultaneous programming of multiple sub-blocks in NAND memory structures | Ali Khakifirooz, Pranav Kalavade, Shantanu R. Rajwade | 2025-06-17 |
| 12322455 | Program verify process having placement aware pre-program verify (PPV) bucket size modulation | Shantanu R. Rajwade, Matin Amani, Narayanan Ramanan, Arun Thathachary | 2025-06-03 |
| 12237023 | Dynamic detection and dynamic adjustment of sub-threshold swing in a memory cell sensing circuit | Shantanu R. Rajwade, Matin Amani, Narayanan Ramanan | 2025-02-25 |
| 11139036 | Using variable voltages to discharge electrons from a memory array during verify recovery operations | Pranav Chava, Shantanu R. Rajwade, Sagar Upadhyay | 2021-10-05 |
| 11094386 | Device, system, and method to verify data programming of a multi-level cell memory based on one of temperature, pressure, wear condition or relative position of the memory cell | Xiang Yang, Narayanan Ramanan, Arun Thathachary, Shantanu R. Rajwade, Matin Amani | 2021-08-17 |
| 11004524 | SSD having a parallelized, multi-level program voltage verification | Xiang Yang, Shantanu R. Rajwade, Ali Khakifirooz | 2021-05-11 |