Issued Patents All Time
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12379989 | Zero voltage program state detection | Kevin Liou | 2025-08-05 |
| 12362016 | Read latency reduction for partially-programmed block of non-volatile memory | Joseph Doller, Noah Mebane | 2025-07-15 |
| 12243590 | Method and apparatus for improving write uniformity in a memory device | Shantanu R. Rajwade, Christian Mion, Pranav Kalavade, Rohit S. Shenoy, Xin Sun | 2025-03-04 |
| 11462273 | SSD with reduced secure erase time and endurance stress | Joseph Doller, Byeongkyu Cho | 2022-10-04 |
| 11163480 | Method and apparatus for performing an erase operation comprising a sequence of micro-pulses in a memory device | Aliasgar S. Madraswala, Siddhanth Munukutla, Tanya Wanchoo, Heonwook Kim | 2021-11-02 |
| 10762974 | One check fail byte (CFBYTE) scheme | Aliasgar S. Madraswala, Naveen Vittal Prabhu, Purval S. Sule, Trupti Bemalkhedkar, Nehul N. Tailor +2 more | 2020-09-01 |
| 10714186 | Method and apparatus for dynamically determining start program voltages for a memory device | Purval S. Sule, Aliasgar S. Madraswala, Shantanu R. Rajwade, Trupti Bemalkhedkar, Leonard Aaron Turcios | 2020-07-14 |
| 10509597 | Memory block access modes for a storage device | Jason H. Culp | 2019-12-17 |
| 10354738 | One check fail byte (CFBYTE) scheme | Aliasgar S. Madraswala, Naveen Vittal Prabhu, Purval S. Sule, Trupti Bemalkhedkar, Nehul N. Tailor +2 more | 2019-07-16 |
| 10340024 | Solid state drive physical block revectoring to improve cluster failure rates | Brian C. Romo | 2019-07-02 |
| 10229057 | Method and apparatus for avoiding bus contention after initialization failure | Aliasgar S. Madraswala, Bharat Pathak | 2019-03-12 |
| 10224107 | Method and apparatus for dynamically determining start program voltages for a memory device | Purval S. Sule, Aliasgar S. Madraswala, Shantanu R. Rajwade, Trupti Bemalkhedkar, Leonard Aaron Turcios | 2019-03-05 |
| 9543019 | Error corrected pre-read for upper page write in a multi-level cell memory | Robert E. Frickey, Yogesh B. Wakchaure, Iwen Chao, Xin Guo | 2017-01-10 |
| 9524774 | Lower page read for multi-level cell memory | Robert E. Frickey, Yogesh B. Wakchaure, Iwen Chao, Xin Guo | 2016-12-20 |
| 9471488 | Techniques for improving reliability and performance of partially written memory blocks in modern flash memory systems | Yogesh B. Wakchaure, Aliasgar S. Madraswala, Charan Srinivasan | 2016-10-18 |
| 9236136 | Lower page read for multi-level cell memory | Robert E. Frickey, Yogesh B. Wakchaure, Iwen Chao, Xin Guo | 2016-01-12 |
| 9208888 | Techniques for improving reliability and performance of partially written memory blocks in modern flash memory systems | Yogesh B. Wakchaure, Aliasgar S. Madraswala, Charan Srinivasan | 2015-12-08 |