Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11749373 | Bad block management for memory sub-systems | — | 2023-09-05 |
| 11424256 | Transistors, semiconductor constructions, and methods of forming semiconductor constructions | Deepak Thimmegowda, Andrew Bicksler | 2022-08-23 |
| 11367502 | Bad block management for memory sub-systems | — | 2022-06-21 |
| 10770156 | Memory devices and methods for read disturb mitigation involving word line scans to detect localized read disturb effects and to determine error count in tracked sub sets of memory addresses | Renato C. Padilla, Jung Sheng Hoei, Michael G. Miller, Sampath K. Ratnam, Kishore Kumar Muchherla +3 more | 2020-09-08 |
| 10726936 | Bad block management for memory sub-systems | — | 2020-07-28 |
| 10510422 | Memory devices with read level calibration | Gary F. Besinga, Peng Fei, Michael G. Miller, Kishore Kumar Muchherla, Renato C. Padilla +3 more | 2019-12-17 |
| 10497707 | Semiconductor constructions which include metal-containing gate portions and semiconductor-containing gate portions | Deepak Thimmegowda, Andrew Bicksler | 2019-12-03 |
| 10340016 | Methods of error-based read disturb mitigation and memory devices utilizing the same | Renato C. Padilla, Jung Sheng Hoei, Michael G. Miller, Sampath K. Ratnam, Kishore Kumar Muchherla +3 more | 2019-07-02 |
| 10199111 | Memory devices with read level calibration | Gary F. Besinga, Peng Fei, Michael G. Miller, Kishore Kumar Muchherla, Renato C. Padilla +3 more | 2019-02-05 |
| 9613978 | Methods of forming semiconductor constructions | Deepak Thimmegowda, Andrew Bicksler | 2017-04-04 |
| 9219132 | Transistors, semiconductor constructions, and methods of forming semiconductor constructions | Deepak Thimmegowda, Andrew Bicksler | 2015-12-22 |
| 8853769 | Transistors and semiconductor constructions | Deepak Thimmegowda, Andrew Bicksler | 2014-10-07 |