Issued Patents All Time
Showing 1–25 of 25 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11768603 | Apparatuses and methods for concurrently accessing multiple partitions of a non-volatile memory | Rajesh Sundaram, Derchang Kau, Daniel Chu, Raymond W. Zeng, Shekoufeh Qawami | 2023-09-26 |
| 11587874 | Resistance reduction for word lines in memory arrays | Sung-Taeg Kang, Pranav Kalavade, Prasanna Srinivasan | 2023-02-21 |
| 11354040 | Apparatuses and methods for concurrently accessing multiple partitions of a non-volatile memory | Rajesh Sundaram, Derchang Kau, Daniel Chu, Raymond W. Zeng, Shekoufeh Qawami | 2022-06-07 |
| 10923450 | Memory arrays with bonded and shared logic circuitry | Richard Fastow, Khaled Hasnat, Prashant Majhi, Krishna K. Parat | 2021-02-16 |
| 10719237 | Apparatuses and methods for concurrently accessing multiple partitions of a non-volatile memory | Rajesh Sundaram, Derchang Kau, Daniel Chu, Raymond W. Zeng, Shekoufeh Qawami | 2020-07-21 |
| 10651153 | Three-dimensional (3D) memory with shared control circuitry using wafer-to-wafer bonding | Richard Fastow, Khaled Hasnat, Prashant Majhi | 2020-05-12 |
| 10515973 | Wordline bridge in a 3D memory array | Deepak Thimmegowda, David S. Meyaard, Khaled Hasnat | 2019-12-24 |
| RE41217 | Method and apparatus for reducing stress across capacitors used in integrated circuits | Ramkarthik Ganesan | 2010-04-13 |
| 6831862 | Method and apparatus for matched-reference sensing architecture for non-volatile memories | Kerry D. Tedrow, Balaji Srinivasan | 2004-12-14 |
| 6515906 | Method and apparatus for matched-reference sensing architecture for non-volatile memories | Kerry D. Tedrow, Balaji Srinivasan | 2003-02-04 |
| 6449211 | Voltage driver for a memory | Rajesh Sundaram, Mase J. Taub, Rupinder K. Bains, Raymond W. Zeng, Binh Ngo +1 more | 2002-09-10 |
| 6418506 | Integrated circuit memory and method for transferring data using a volatile memory to buffer data for a nonvolatile memory array | Richard D. Pashley, Mark Winston, David Kaplan | 2002-07-09 |
| 6297974 | Method and apparatus for reducing stress across capacitors used in integrated circuits | Ramkarthik Ganesan | 2001-10-02 |
| 5802552 | System and method for allocating and sharingpage buffers for a flash memory device | Mickey L. Fandrich, Mamun Ur Rashid, Richard J. Durante | 1998-09-01 |
| 5621690 | Nonvolatile memory blocking architecture and redundancy | Mark Winston | 1997-04-15 |
| 5430677 | Architecture for reading information from a memory array | Mickey L. Fandrich | 1995-07-04 |
| 5414829 | Override timing control circuitry and method for terminating program and erase sequences in a flash memory | Mickey L. Fandrich | 1995-05-09 |
| 5390146 | Reference switching circuit for flash EPROM | Gregory E. Atwood | 1995-02-14 |
| 5386388 | Single cell reference scheme for flash memory sensing and program state verification | Gregory E. Atwood, Neal R. Mielke, Branislav Vajdic | 1995-01-31 |
| 5363335 | Nonvolatile memory with automatic power supply configuration | Thomas C. Price | 1994-11-08 |
| 5265059 | Circuitry and method for discharging a drain of a cell of a non-volatile semiconductor memory | Steven Wells, Mickey L. Fandrich | 1993-11-23 |
| 5249158 | Flash memory blocking architecture | Virgil N. Kynett, Mickey L. Fandrich, Steven Wells, Kurt B. Robinson | 1993-09-28 |
| 4975883 | Method and apparatus for preventing the erasure and programming of a nonvolatile memory | Alan E. Baker, Richard J. Durante | 1990-12-04 |
| 4875188 | Voltage margining circuit for flash eprom | — | 1989-10-17 |
| 4858186 | A circuit for providing a load for the charging of an EPROM cell | — | 1989-08-15 |