Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Memory devices with four data line bias levels

Memory devices with four data line bias levels

US Patent 11562791 · Granted Jan 24, 2023

Estimated economic value: $10,431,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Memory device producing metadata characterizing applied read voltage level with 2025
Capacitive sensing with a micro pump in a memory device2025
Fast bit erase for upper tail tightening of threshold voltage distributions2025
Fast bit erase for upper tail tightening of threshold voltage distributions2025
Fast bit erase for upper tail tightening of threshold voltage distributions2025
Corrective reads implementing incremental reads with respect to adjacent wordlin2025
Volatile data storage in NAND memory2025
Volatile data storage in NAND memory2025
Volatile data storage in NAND memory2025
Charge loss acceleration during programming of memory cells in a memory sub-syst2025
Charge loss acceleration during programming of memory cells in a memory sub-syst2025
Status polling based on die-generated pulsed signal2025